Non-binary codes are highly efficient error-correcting codes for short message sizes. They are also naturally adapted to coded modulations, and therefore, can be used to approach channel capacity. However, non-binary decoders built on sets of high cardinalities (greater than or equal to 64) are still marginally used due to their high decoding complexity. This thesis studies and proposes new algorithms for simplifying the processing of the parity nodes for two types of non-binary error- correcting codes: Non-Binary Low-Density Parity Check (NB-LDPC) and Non-Binary Polar Codes (NB-PC). For NB-LDPC codes, a new decoding technique called the Best-Request-Default (BRD) algorithm has been proposed. In the context of truncated message exchange, it becomes interesting to relax the extrinsic information principle and make messages exchanged over a connection between a variable node and a parity node interdependent. More precisely, part of the parity node's processing will be dedicated to responding to the "requested" symbols by the variable node (the algorithm's "request" term). The BRD algorithm makes it possible to significantly reduce the size of the messages exchanged, and therefore the complexity of the decoder, without any significant degradation in performance. The decoding of high-cardinality NB-PC codes is still a largely unexplored field, and the state-of- the-art consists of adapting the Extended Min-Sum algorithm developed for NB-LDPC codes to NB-PC codes. We propose two new optimizations: firstly, a reduction in the complexity of parity node processing through asymmetrical processing of its inputs based on a relative reliability criterion (Asymmetrical Extended Min-Sum algorithm), and secondly, an ad-hoc simplification of each parity constraint according to the polarization of the messages arriving at it (Polarization- Aware Polar Decoder). The combination of these two optimizations reduces complexity by a factor of 2 compared with the state-of-the-art, again without any noticeable degradation in decoding performance.
Non-binary codes are highly efficient error-correcting codes for short message sizes. They are also naturally adapted to coded modulations, and therefore, can be used to approach channel capacity. However, non-binary decoders built on sets of high cardinalities (greater than or equal to 64) are still marginally used due to their high decoding complexity. This thesis studies and proposes new algorithms for simplifying the processing of the parity nodes for two types of non-binary error- correcting codes: Non-Binary Low-Density Parity Check (NB-LDPC) and Non-Binary Polar Codes (NB-PC). For NB-LDPC codes, a new decoding technique called the Best-Request-Default (BRD) algorithm has been proposed. In the context of truncated message exchange, it becomes interesting to relax the extrinsic information principle and make messages exchanged over a connection between a variable node and a parity node interdependent. More precisely, part of the parity node's processing will be dedicated to responding to the "requested" symbols by the variable node (the algorithm's "request" term). The BRD algorithm makes it possible to significantly reduce the size of the messages exchanged, and therefore the complexity of the decoder, without any significant degradation in performance. The decoding of high-cardinality NB-PC codes is still a largely unexplored field, and the state-of- the-art consists of adapting the Extended Min-Sum algorithm developed for NB-LDPC codes to NB-PC codes. We propose two new optimizations: firstly, a reduction in the complexity of parity node processing through asymmetrical processing of its inputs based on a relative reliability criterion (Asymmetrical Extended Min-Sum algorithm), and secondly, an ad-hoc simplification of each parity constraint according to the polarization of the messages arriving at it (Polarization- Aware Polar Decoder). The combination of these two optimizations reduces complexity by a factor of 2 compared with the state-of-the-art, again without any noticeable degradation in decoding performance.
Optimisation algorithmique des décodeurs non-binaires Les codes non binaires sont des codes correcteurs d'erreurs très efficaces pour les petites tailles de message. Ils sont de plus naturellement adapté aux modulations codées et permettent ainsi de s'approcher de la capacité du canal. Toutefois, les décodeurs non binaires construit sur des ensembles de cardinalité élevée (supérieure ou égale à 64) sont encore marginalement utilisés dû à leur grande complexité de décodage. Cette thèse étudie et propose de nouveaux algorithmes de simplification du traitement des nœuds de parités pour deux types de codes correcteurs d'erreur Non-Binaire : les codes Low Density Parity Check non-binaire (NB-LDPC) et les codes polaire Non- Binaire (NB-PC). Pour les codes NB-LDPC, une nouvelle technique de décodage appelée "algorithme Best- Request-Default" (BRD) a été proposée. Dans un contexte d'échange de messages tronquées, il devient intéressant de relaxer le principe d'information extrinsèque et de rendre interdépendants les messages échangés sur une connexion entre un nœud de variable et un nœud de parité. Plus précisément, une partie du traitement du nœud de parité sera dédié pour fournir une réponse aux symboles "demandés" par le nœud de variable (terme "request" de l'algorithme). L'algorithme BRD permet de réduire très significativement la taille des messages échangés, et donc, la complexité du décodeur, et ce, sans dégradation significative de performances. Le décodage de code NB-PC de grande cardinalité est un domaine encore très peu exploré et l'état de l'art consiste à l'adaptation de l'algorithme Extended Min-Sum développé pour les codes NB-LDPC aux codes NB-PC. Nous proposons deux optimisations nouvelles : d'une part, une réduction de la complexité du traitement nœud de parité par un traitement asymétrique de ses entrées basés sur un critère de fiabilité relative (algorithme Asymmetrical Extended Min-Sum), d'autre part, une simplification ad-hoc de chaque contrainte de parité en fonction de la polarisation des messages lui arrivant (Polarisation Aware Polar Code Decoder). La combinaison de ces deux optimisations permet de réduire la complexité d'un facteur 2 par rapport à l'état de l'art, de nouveau sans dégradation notable des performances de décodage.
In this thesis, we propose low-complexity designing algorithms for non-binary low-density
parity-check (NB-LDPC) codes over GF(q) with low error floor and low-complexity decoding
algorithms for binary LDPC codes.
We first propose a low-complexity designing algorithm for for NB-LDPC codes over GF(q)
based on message-passing algorithms. Short cycles in an NB-LDPC code may be even
more harmful to its performance if they do not satisfy the so-called full rank condition
(FRC). This is because they may induce low-weight codewords or absorbing sets in that
case. Thus, it is crucial to count the number of short cycles not satisfying the FRC as well as
the number of short cycles for analyzing the performance of an NB-LDPC code. In order to
count those cycles, we first develop a novel message-passing algorithm and identify how it
is related to the FRC.We then propose a low-complexity algorithmfor counting the number
of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short
cycles. The proposed algorithm is not only theoretically validated, but its computational
and storage complexities are also computed. It does not require cycle enumeration with
high complexity, and therefore is still feasible even in the case of large code length, say
≤ 5000, unlike the conventional methods. Based on it, we also provide a locally optimal
rule to choose a nonzero element for a given edge and propose a low-complexity algorithm
for designing an NB-LDPC code with low error floor. Furthermore, several design examples
are presented to verify the validity of the proposed design algorithm.
Secondly, we propose a low-complexity decoding algorithm for binary LDPC codes over
the binary symmetric channel (BSC). The min-sum (MS) algorithm is a low-complexity decoding
algorithm for binary LDPC codes and has lower computational complexity than the
sum-product algorithm (SPA). Since the MS algorithm is an approximation of the SPA, it
has performance degradation. Furthermore, reducing the number of bits for representing
messages to two in a decoding algorithm for further reducing computational and storage
complexities, causes significant performance losses. In order to minimize the performance
degradation and computational and storage complexities, we propose a low-complexity
decoding algorithm which uses several decoders with two-bit precision for binary LDPC
codes over the BSC. The proposed algorithm adaptively changes decoders according to
the number of unsatisfied check nodes at each iteration. Compared with the SPA using
floating-point operations, the proposed decoding algorithm greatly reduces computational
and storage complexities with negligible performance losses. Numerical results show that
the proposed decoding algorithm has similar performance to the SPA with floating-point
operations over the BSC.
In the last part of this thesis, low-complexity decoding algorithms of binary LDPC codes
for the core layer at fixed receivers in ATSC 3.0 are proposed. Gallager’s decoding algorithms
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Low Density Parity Check (LDPC) codes over a Galois Field GF(q) can provide significantly better error- correcting quality than binary LDPC codes with moderate code length. However, the computational complexity and memory requirement of nonbinary codes are much higher, limiting the application of non- binary LDPC codes. In this paper, we propose an adaptive message truncation algorithm for non-binary LDPC decoding, guided by the estimated code error rates. Compared to the previous fixed message truncation method, it can cut the messages adaptively, and therefore provide better decoding quality and computation complexity reduction. To further reduce the computation, we propose another adaptive check node update algorithm, simplifying the decoding by reducing the number of check nodes updating. Our simulation results demonstrate that by combining these two algorithms together, the average message size can be reduced greatly and good decoding quality is achieved, at a little cost of iterations. Compared to the existing truncation algorithms, our approach can reduce the order of complexity to O(nalog2(na)) (where nais messages size), with less performance degradation.
Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a novel relaxed check node processing scheme is proposed for the min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p) can be uniquely represented by a linear combination of p independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then, the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and the overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25) can achieve 52% higher efficiency in terms of throughput-over-area ratio.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding algorithm. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as “compressed” c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code overGF(25) can achieve the same throughput with only 46% of the area.
This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures.\n\nA new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. \n\nIn order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. \n\nFinally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.