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IEEE International Conference on Quantum Computing and Engineering (QCE)

Moveless: Minimizing QEC Overhead on QCCDS via Versatile Execution and Low Excess Shuttling

Sahil Khan, Suhas Vittal, Kenneth R. Brown, Jonathan Baker

Published Aug 30, 2025• 0 citations
Publisher

Abstract

One of the most promising paths towards large scale fault tolerant quantum computation is the use of quantum error correcting codes. The majority of popular codes are stabilizer codes, in which error information is extracted via the repeated execution of a set of commuting stabilizer measurement circuits and then decoded. Just like every other quantum circuit, these circuits must be compiled to hardware in a way to minimize the total physical error introduced into the system, for example either due to high latency execution or excessive gates to meet connectivity limitations of the target hardware. However, unlike arbitrary quantum circuits, all syndrome extraction circuits have several common properties, for example they have a bipartite connectivity graph, consist only of commuting subcircuits, and have a set of ancilla which are indistinguishable between measurement rounds, among others. For the most part, compilation methods have aimed at being generic, able to map any input circuit into executables on the hardware, and therefore cannot appropriately exploit these properties and result in executables which have higher physical error. In the case of modular trapped ion systems, specifically QCCDs, this corresponds to the insertion of excessive shuttling operations necessary to realize arbitrary qubit interactions. We propose a compilation scheme explicitly tailored for the structural regularity of quantum error correction code physical circuits, with the primary objective of minimizing circuit latency from shuttling operations. Our compiler's success is predicated on several key observations: 1. only ancilla or data (but not both) should be shuttled, 2. stabilizers can be executed in any order meaning we can dynamically modify circuit execution on a per-cycle basis 3. ancilla are indistinguishable meaning any can be selected to begin a stabilizer measurement and since only ancilla are shuttled, we retain a fixed-point mapping between cycles, and 4. QCCD hardware limits the number of parallel operations equal to the number traps in the system bounding the rate of stabilizer measurement meaning fewer ancilla are necessary and can be easily reused. Our resulting compiler, leads to QEC circuits which are on average$3.38 \times$faster to execute (by up to$5.24 \times$) and therefore incur lower physical error. For codes with good decoders, e.g. the color code and surface code, these improvements lead to up to two orders of magnitude of improvement in logical error rates with realistic physical error rates.

DOI
10.1109/qce65121.2025.00075

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One of the most promising paths towards large scale fault tolerant quantum computation is the use of quantum error correcting codes. The majority of popular codes are stabilizer codes, in which error information is extracted via the repeated execution of a set of commuting stabilizer measurement circuits and then decoded. Just like every other quantum circuit, these circuits must be compiled to hardware in a way to minimize the total physical error introduced into the system, for example either due to high latency execution or excessive gates to meet connectivity limitations of the target hardware. However, unlike arbitrary quantum circuits, all syndrome extraction circuits have several common properties, for example they have a bipartite connectivity graph, consist only of commuting subcircuits, and have a set of ancilla which are indistinguishable between measurement rounds, among others. For the most part, compilation methods have aimed at being generic, able to map any input circuit into executables on the hardware, and therefore cannot appropriately exploit these properties and result in executables which have higher physical error. In the case of modular trapped ion systems, specifically QCCDs, this corresponds to the insertion of excessive shuttling operations necessary to realize arbitrary qubit interactions. We propose a compilation scheme explicitly tailored for the structural regularity of quantum error correction code physical circuits, with the primary objective of minimizing circuit latency from shuttling operations. Our compiler's success is predicated on several key observations: 1. only ancilla or data (but not both) should be shuttled, 2. stabilizers can be executed in any order meaning we can dynamically modify circuit execution on a per-cycle basis 3. ancilla are indistinguishable meaning any can be selected to begin a stabilizer measurement and since only ancilla are shuttled, we retain a fixed-point mapping between cycles, and 4. QCCD hardware limits the number of parallel operations equal to the number traps in the system bounding the rate of stabilizer measurement meaning fewer ancilla are necessary and can be easily reused. Our resulting compiler, leads to QEC circuits which are on average3.38×3.38 \times3.38×faster to execute (by up to5.24×5.24 \times5.24×) and therefore incur lower physical error. For codes with good decoders, e.g. the color code and surface code, these improvements lead to up to two orders of magnitude of improvement in logical error rates with realistic physical error rates.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding. This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Logical qubits can be protected from decoherence by performing quantum error-correction (QEC) cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory that operates for in principle arbitrary long times. All circuit components must be assumed as noisy unless specific assumptions about the form of the noise are made. Modern QEC schemes are challenging to implement experimentally in physical architectures where in-sequence measurements and feed forward of classical information cannot be reliably executed fast enough or even at all. Here we provide a novel scheme to perform QEC cycles without the need of measuring qubits that is fully fault-tolerant with respect to all components used in the circuit. Our scheme can be used for any low-distance CSS code since its only requirement towards the underlying code is a transversal gate. Similarly to Steane-type EC, we coherently copy errors to a logical auxiliary qubit but then apply a coherent feedback operation from the auxiliary system to the logical data qubit. The logical auxiliary qubit is prepared fault tolerantly without measurements, too. We benchmark logical failure rates of the scheme in comparison to a flag-qubit-based EC cycle. We map out a parameter region where our scheme is feasible and estimate physical error rates necessary to achieve the break-even point of beneficial QEC with our scheme. We outline how our scheme could be implemented in ion traps and with neutral atoms in a tweezer array. For recently demonstrated capabilities of atom shuttling and native multiatom Rydberg gates, we achieve moderate circuit depths and beneficial performance of our scheme while not breaking fault tolerance. These results thereby enable practical fault-tolerant QEC in hardware architectures that do not support midcircuit measurements. Published by the American Physical Society 2024
Quantum error correction (QEC) codes are traditionally defined and searched for without specifying the manner in which its syndrome extraction circuits are executed using elementary gates and measurements. We show how morphing circuits introduced in Refs. [1-3] provide a way of optimising syndrome extraction circuits and codes directly in terms of connectivity, choice of two-qubit gate (ISWAP versus CNOT) and number of physical qubits. We discuss morphing circuits in code optimisation among Abelian two-block group algebra (2BGA) codes, handling boundaries for 2D codes, codes with single-shot properties, and improving performance in stability experiments against measurement and reset errors. We show that alternating syndrome extraction circuits - executed with alternating time-reversed rounds - can be viewed as a two-round morphing circuit whose fault-tolerant properties are computationally much easier to examine than non-alternating syndrome extraction circuits. Our methods find new codes and syndrome extraction circuits of practical interest, including Abelian 2BGA morphing circuits with better code parameters and connectivity than existing circuits. [1] Matt McEwen, Dave Bacon, and Craig Gidney. Relaxing hardware requirements for surface code circuits using time-dynamics. Quantum, 7:1172, 2023. [2] Craig Gidney and Cody Jones. New circuits and an open source decoder for the color code, 2023. [3] Mackenzie H. Shaw and Barbara M. Terhal. Lowering connectivity requirements for bivariate bicycle codes using morphing circuits.
Modular trapped-ion quantum computing hardware, known as QCCDs require shuttling operations in order to maintain effective all-to-all connectivity. Each module or trap can perform only one operation at a time, resulting in low intra-trap parallelism, but there is no restriction on operations happening on independent traps, enabling high inter-trap parallelism. Unlike their superconducting counterparts, the design space for QCCDs is relatively flexible and can be explored beyond current grid designs. In particular, current grid-based architectures significantly limit the performance of many promising, high-rate codes such as HGP codes and BB codes, suffering from numerous trap to trap ``roadblocks", forcing serialization and destroying the inherent parallelism of these codes.. Many of these codes are highly parallelizable, meaning that with appropriate hardware layouts and matching software schedules, execution latency can be reduced. Faster execution, in turn, reduces error accumulation from decoherence and heating, ultimately improving code performance when mapped to realistic hardware. To address this, we propose Cyclone, a circular software-hardware codesign that departs from traditional 2D grids in favor of a flexible ring topology, where ancilla qubits move in lockstep. Cyclone eliminates roadblocks, bounds total movement, and enables high levels of parallelism, resulting in up to ~4×\times× speedup in execution times. With HGP codes, Cyclone achieves up to a 2×\times× order of magnitude improvement in logical error rate, and with BB codes, this improvement reaches up to a 3×\times× in order of magnitude.Spatially, Cyclone reduces the number of required traps and ancilla qubits by 2×2\times2×.The overall spacetime improvement over a standard grid is up to ∼20×\sim 20 \times∼20×, demonstrating Cyclone as a scalable and efficient alternative to conventional 2D QCCD architectures.
Color codes are promising quantum error-correction (QEC) codes because they have an advantage over surface codes in that all Clifford gates can be implemented transversally. However, the thresholds of color codes under circuit-level noise are relatively low, mainly because measurements of their high-weight stabilizer generators cause an increase in the circuit depth and, thus, substantial errors are introduced. This makes color codes not the best candidate for fault-tolerant quantum computing. Here, we propose a method to suppress the impact of such errors by optimizing weights of decoders using conditional error probabilities conditioned on the measurement outcomes of flag qubits. In numerical simulations, we improve the threshold of the (4.8.8) color code under circuit-level noise from 0.14% to around 0.27%, which is calculated by using an integer programming decoder. Furthermore, in the (6.6.6) color code, we achieve a circuit-level threshold of around 0.36%, which is almost the same value as the highest value in the previous studies employing the same noise model. In both cases, the effective code distance is also improved compared to a conventional method that uses a single ancilla qubit for each stabilizer measurement. Thereby, the achieved logical error rates at low physical error rates are almost one order of magnitude lower than those of the conventional method with the same code distance. Even when compared to the single-ancilla method with a higher code distance, considering the increased number of qubits used in our method, we achieve lower logical error rates in most cases. This method can also be applied to other weight-based decoders, making the color codes more promising as candidates for the experimental implementation of QEC. Furthermore, one can utilize this approach to improve a threshold of wider classes of QEC codes, such as high-rate quantum low-density parity-check codes. Published by the American Physical Society 2024
Shuttling-based trapped-ion quantum computers (QCCD) rank among the most mature hardware platforms. Existing and envisaged devices exhibit architectural differences in terms of register layout and connectivity. Platform-specific compilers are required to translate quantum circuits into resource-optimized hardware-level command chains. Hardware platforms and compiler software stacks are mostly developed independently of one another by different research communities. This work aims to bridge these communities by abstracting QCCD architectures and native operations, enabling computer scientists to address compilation problems using generic methods without requiring a deep background in the physical operating principles of the platform. The resulting design space is organized into a small set of architectural archetypes, each posing its own compilation problem. We then select and apply compilation methods to one- and two-dimensional QCCD architectures, finding that the routing overhead scales approximately cubically with the number of qubits for the one-dimensional architecture and approximately quadratically for the two-dimensional one. Extending this to compilation with a quantum error-correction layer reveals additional differences and similarities between the physical and logical levels. We conclude that co-design is a requirement rather than an option, and this work provides the vocabulary, archetypes, and compilation abstraction it needs.