The drastic growth of data generation by companies such as Google and Facebook, the widespread integration of IoT devices into everyday life, advancements in artificial intelligence, and the rise of social media platforms are driving a shift from model-driven to data-driven science. This surge in data created a need for massively parallel accelerators such as graphics processing units (GPU). High Performance Computing (HPC) are required to accommodate the growing complexity of data-driven technologies. HPC demands are anticipated to reach exascale levels within this decade. Since 2004, three waves of high-performance accelerators have driven advancements in HPC: the first wave introduced Central Processing Units (CPUs) and Field Programmable Gate Arrays (FPGAs), the second wave brought General Purpose Graphics Processing Units (GPGPUs), and the third wave focused on machine learning specific GPUs. Recent research reveals that quantum processing units (QPUs) have the potential to be the fourth wave of high-performance acceleration in the near future. However, as Quantum Computing is still in its early stages, its practical and useful quantum computation is yet to be developed. In this paper, a heterogeneous CPU-GPU-QPU (HCGQ) accelerator is proposed. The accelerator is based on an input size threshold, where the CPU assigns smaller input sizes workloads to the GPU, and larger input sizes to the QPU. This dynamic workload allocation is realized entirely through software-level integration. Using the searching algorithm and deep neural networks as benchmarks, it was observed that the HCGQ accelerator outperformed standalone GPUs and QPUs in terms of speed and energy efficiency.
The drastic growth of data generation by companies such as Google and Facebook, the widespread integration of IoT devices into everyday life, advancements in artificial intelligence, and the rise of social media platforms are driving a shift from model-driven to data-driven science. This surge in data created a need for massively parallel accelerators such as graphics processing units (GPU). High Performance Computing (HPC) are required to accommodate the growing complexity of data-driven technologies. HPC demands are anticipated to reach exascale levels within this decade. Since 2004, three waves of high-performance accelerators have driven advancements in HPC: the first wave introduced Central Processing Units (CPUs) and Field Programmable Gate Arrays (FPGAs), the second wave brought General Purpose Graphics Processing Units (GPGPUs), and the third wave focused on machine learning specific GPUs. Recent research reveals that quantum processing units (QPUs) have the potential to be the fourth wave of high-performance acceleration in the near future. However, as Quantum Computing is still in its early stages, its practical and useful quantum computation is yet to be developed. In this paper, a heterogeneous CPU-GPU-QPU (HCGQ) accelerator is proposed. The accelerator is based on an input size threshold, where the CPU assigns smaller input sizes workloads to the GPU, and larger input sizes to the QPU. This dynamic workload allocation is realized entirely through software-level integration. Using the searching algorithm and deep neural networks as benchmarks, it was observed that the HCGQ accelerator outperformed standalone GPUs and QPUs in terms of speed and energy efficiency.
High-performance computing (HPC) has evolved over decades through multiple architectural transitions, from vector supercomputers to massively parallel CPU clusters and GPU-accelerated systems, continuously expanding the frontier of scientific discovery. With the emergence of quantum processing units (QPUs) as practical computational accelerators, a new opportunity arises to further extend this trajectory by integrating quantum and classical computing paradigms. Building on the emerging vision of Quantum Integrated High-Performance Computing (QHPC), this paper contributes a full-stack layered architecture that integrates QPUs as first-class accelerators within, not merely alongside, the classical HPC software and hardware stack, with tight, on-premise quantum–classical coupling as its defining characteristic. The architecture comprises of unified resource management, quantum-aware scheduling, hybrid workflow orchestration, middleware and programming abstraction, interconnect technologies, and a tiered execution model enabling seamless workload partitioning across classical and quantum backends. A central aspect of this architecture is a strong user requests abstraction layer that exposes heterogeneous resources through a unified job submission interface, similar in spirit to existing schedulers such as Slurm, allowing users to describe workloads in a consistent template independent of underlying compute type or location. Drawing insights from prior accelerator integration eras, we outline how QHPC can support emerging workloads in quantum chemistry, materials discovery, combinatorial optimization, and climate modeling. We conclude by highlighting open challenges in building scalable, reliable, and programmable quantum–classical infrastructures that seamlessly connect global users to heterogeneous compute resources for future quantum–classical HPC ecosystems.
High-performance computing (HPC) has evolved over decades through multiple architectural transitions, from vector supercomputers to massively parallel CPU clusters and GPU-accelerated systems, continuously expanding the frontier of scientific discovery. With the emergence of quantum processing units (QPUs) as practical computational accelerators, a new opportunity arises to further extend this trajectory by integrating quantum and classical computing paradigms. Building on the emerging vision of Quantum Integrated High-Performance Computing (QHPC), this paper contributes a full-stack layered architecture that integrates QPUs as first-class accelerators within, not merely alongside, the classical HPC software and hardware stack, with tight, on-premise quantum-classical coupling as its defining characteristic. The architecture comprises of unified resource management, quantum-aware scheduling, hybrid workflow orchestration, middleware and programming abstraction, interconnect technologies, and a tiered execution model enabling seamless workload partitioning across classical and quantum backends. A central aspect of this architecture is a strong user requests abstraction layer that exposes heterogeneous resources through a unified job submission interface, similar in spirit to existing schedulers such as Slurm, allowing users to describe workloads in a consistent template independent of underlying compute type or location. Drawing insights from prior accelerator integration eras, we outline how QHPC can support emerging workloads in quantum chemistry, materials discovery, combinatorial optimization, and climate modeling. We conclude by highlighting open challenges in building scalable, reliable, and programmable quantum-classical infrastructures that seamlessly connect global users to heterogeneous compute resources for future quantum-classical HPC ecosystems.
High-Performance Computing (HPC) has historically served as the primary engine for scientific advancement, enabling complex simulations ranging from meteorological prediction to protein folding or drug discovery. For decades, the exponential growth in computational power was sustained by the empirical axioms of Moore’s Law and Dennard scaling. However, in the last decade, these principles have begun to exhibit unambiguous signs of saturation. The fundamental physical, thermodynamic, and quantum limitations of silicon transistors have compelled the industry to abandon frequency scaling in favor of massive parallelism and architectural heterogeneity. Consequently, contemporary top-tier supercomputers are no longer homogeneous machines, but complex clusters that integrate multicore Central Processing Units (CPU) with specialized accelerators such as Graphics Processing Units (GPU) or FPGAs.
Quantum computers have demonstrated utility in simulating quantum systems beyond brute-force classical approaches. As the community builds on these demonstrations to explore using quantum computing for applied research, algorithms and workflows have emerged that require leveraging both quantum computers and classical high-performance computing (HPC) systems to scale applications, especially in chemistry and materials, beyond what either system can simulate alone. Today, these disparate systems operate in isolation, forcing users to manually orchestrate workloads, coordinate job scheduling, and transfer data between systems -- a cumbersome process that hinders productivity and severely limits rapid algorithmic exploration. These challenges motivate the need for flexible and high-performance Quantum-Centric Supercomputing (QCSC) systems that integrate Quantum Processing Units (QPUs), Graphics Processing Units (GPUs), and Central Processing Units (CPUs) to accelerate discovery of such algorithms across applications. These systems will be co-designed across quantum and classical HPC infrastructure, middleware, and application layers to accelerate the adoption of quantum computing for solving critical computational problems. We envision QCSC evolution through three distinct phases: (1) quantum systems as specialized compute offload engines within existing HPC complexes; (2) heterogeneous quantum and classical HPC systems coupled through advanced middleware, enabling seamless execution of hybrid quantum-classical algorithms; and (3) fully co-designed heterogeneous quantum-HPC systems for hybrid computational workflows. This article presents a reference architecture and roadmap for these QCSC systems.
The exponential growth of large language models (LLMs) and deep neural networks has pushed conventional GPUbased compute infrastructures toward fundamental physical and economic limits. While graphics processing units (GPUs) remainthe dominant platform for AI training and inference, emerging hardware paradigms—particularly quantum computing processors and neuromorphic chips—promise transformative gains in energy efficiency, parallelism, and computational throughput.This paper presents a systematic comparative analysis of three leading hardware classes: high-performance GPUs (NVIDIA H100, AMD MI300X), gate-based quantum processors (IBM Eagle, Google Sycamore), and neuromorphic processors (Intel Loihi 2, IBM TrueNorth). We evaluate these architectures across five critical dimensions: raw throughput, energy efficiency, scalability, programmability, and readiness for production AI workloads. Our analysis demonstrates that while GPUs maintain decisive advantages for transformer-based workloads through 2027, quantum annealers exhibit compelling potential for combinatorial optimization in neural architecture search, and neuromorphic chips offer orders-of-magnitude improvements in energy efficiency for sparse, event-driven inference tasks. We conclude with a proposed hybrid hardware stack and a technology readiness roadmap for the 2025–2035 decade, offering practical guidance for AI systems architects and researchers navigating the post-Moore’s Law compute landscape.
Quantum computing simulation on a classical computer is difficult due to the exponential runtime and memory overhead. Previous work addresses the difficulty by utilizing multiple Graphical Processing Units (GPUs) and multi-node computers. GPUs are efficient for handling runtime issues but have limited total accessible memory space. Meanwhile, the memory of a multi-node computer can be scaled to the petabytes order, but its bandwidth for access from host computers (CPUs) is narrow. To simultaneously accelerate simulation and enlarge the total memory space, we propose a heterogeneous parallelization approach by combining GPUs and CPUs. Our simulator allocates memory to the GPUs first, and then to the CPUs. It thus accelerates simulation by using the full capabilities of the GPUs if memory for the simulation fits in the GPUs on a cluster. Allocating memory to the CPUs reduces benefits of the GPUs but enlarges the capacity of qubits in the simulation. In such case, it can exploit the memory of the GPUs to add one more qubit in the simulation if the size of memory in a node is the power of two (such as 512GB). We show empirical performance evaluations of our simulator in a distributed environment of POWER9.