One kind of logic architecture, known as reversible logic, maps the output and input vectors one-to-one. According to the Landauer’s principle from 1961, if a device is irreversible in its characteristics, then deleting a small amount will cause the release of heat energy of the order of kTln2 joules. Here, T represents the absolute temperature of the environment, and k is referred to as the Boltzmann constant. Quantum logic gates, which each carry out a fundamental unitary operation on 1, 2, or more qubits–two-state quantum systems–can be conceived of as the building blocks of a quantum computer, or as kinfolk’s networks of quantum. Quantum networks need the use of reversible logic components. The multiplication procedure in this study makes use of KMD gates. The KMD gate can be used to create a variety of logic circuits, including AND, half adder, and full adder. The criteria for reversibility, fault tolerance, and universality are satisfied by these gates. This research presents the design and simulation of a unique reversible fault-tolerant Wallace multiplier, Baugh-Wooley multiplier, Vedic multiplier, and minimal complexity multiplier. The above multipliers are designed to obtain the addition and product terms with the least amount of delay and optimal slice utilization for sustainable technology. The complete design of the fundamental reversible logic gates was confirmed using the QCADesigner software version 2.0.3. The current designs of several multipliers are compared in this paper based on a number of parameters, such as garbage output (GO), gate count (GC), quantum cost (QC), area, and constant input (CI). The simulation results show improvements in area, delay, CIs, GO, QC, and GC over currently available architectures.
One kind of logic architecture, known as reversible logic, maps the output and input vectors one-to-one. According to the Landauer’s principle from 1961, if a device is irreversible in its characteristics, then deleting a small amount will cause the release of heat energy of the order of kTln2 joules. Here, T represents the absolute temperature of the environment, and k is referred to as the Boltzmann constant. Quantum logic gates, which each carry out a fundamental unitary operation on 1, 2, or more qubits–two-state quantum systems–can be conceived of as the building blocks of a quantum computer, or as kinfolk’s networks of quantum. Quantum networks need the use of reversible logic components. The multiplication procedure in this study makes use of KMD gates. The KMD gate can be used to create a variety of logic circuits, including AND, half adder, and full adder. The criteria for reversibility, fault tolerance, and universality are satisfied by these gates. This research presents the design and simulation of a unique reversible fault-tolerant Wallace multiplier, Baugh-Wooley multiplier, Vedic multiplier, and minimal complexity multiplier. The above multipliers are designed to obtain the addition and product terms with the least amount of delay and optimal slice utilization for sustainable technology. The complete design of the fundamental reversible logic gates was confirmed using the QCADesigner software version 2.0.3. The current designs of several multipliers are compared in this paper based on a number of parameters, such as garbage output (GO), gate count (GC), quantum cost (QC), area, and constant input (CI). The simulation results show improvements in area, delay, CIs, GO, QC, and GC over currently available architectures.
Background/Objectives: The objective is to reduce the Quantum Cost (QC), Garbage Output (GO) and Gate Counts in the design of the adder by incorporating the Novel Reversible Gates. Methods/Statistical Analysis: In recent day’s energy dissipation is the major complex problem in circuit designing in order to recede this problem the reversible logic is employed, where the input vectors can be derived from the output vectors and from the output vectors the input vectors can be procured. Using this technique the Quantum Cost, Garbage Outputs and Gate Counts of the design is reduced. Findings: Based on the technique of reversible logic a novel reversible Gates is proposed from that the novel reversible adders have been designed. The novel reversible gates satisfy the property of reversibility and universality which shows the uniqueness of the proposed gates. The comparative analysis have been made with the existing work, the proposed work shows a significant improvement in the design optimization parameters. Application/Improvements: The proposed structures can be employed in the ALU design and in Floating Point Multiplier design. The comparative analysis shows that Number of Gates, Garbage Outputs and Quantum Cost is minimum for the proposed gate based structure rather than conventional one Keywords: Garbage Outputs (GO), QCA, Quantum Cost (QC), Reversibility, Reversible Logic, Universality.
Abstract Quantum computing has attracted increased attention in recent years owing to substantial advancements in quantum algorithms and system architecture. Quantum algorithms are implemented using quantum circuits. These circuits include an intrinsic reversibility and often have a substantial Boolean component that requires synthesis. A crucial characteristic of reversible circuits is the preservation of parity. Parity-preserving logic is a category that maintains the parity of both inputs and outputs, facilitating the detection of permanent and transient errors. Multiplier circuits are essential components in digital computing systems, playing a crucial role in the development of various hardware, including arithmetic circuits. This paper first introduces a novel block based on a transformationbased synthesis technique from the elementary quantum gates. Then it proposes a distinctive 2×2 parity-preserving reversible quantum Vedic multiplier based on the recommended block and prior gates. In addition, further designs of Vedic multipliers are provided, encompassing 4-bit, 8-bit, and 16-bit configurations. We illustrate that our design brings superior outcomes regarding quantum cost (QC), constant inputs (CI) count, CNOT-V/V + count, garbage outputs (GO) count, and gate count (GC) in comparison to earlier designs. This study achieves an average decrease of 23.09%, 37.51%, 37.51%, 54.89%, and 19.38% in QC, CI, GO, GC, and CNOT-V/V + count, respectively. Furthermore, all suggested circuits undergo appraisal and validation within the IBM quantum laboratory.
Quantum computers provide considerable potential to enhance computing technology, anticipated to surpass conventional computers by resolving intricate challenges that existing systems cannot tackle. They use quantum algorithms for improved performance and depend on reversible computations based on quantum physics and linear algebra. In contrast to traditional computing, which may include irreversible processes, quantum computing relies on unitary operations that are fundamentally reversible. The parity-preserving feature enables the identification of both permanent and transient defects within circuits. The parity-preserving feature ensures that the input and output states are equal in reversible circuits. Vedic multipliers offer a crucial foundation in the design and implementation of digital circuits, recognized for their speed, efficiency, ease of calculations, reduction of errors, and broad applicability. Prior investigations of quantum Vedic multipliers have faced obstacles like elevated Quantum Cost (QC), substantial Garbage Output (GO), Constant Input (CI), augmented Gate Count (GC), and CNOT-V/V+ count, resulting in more resource use and implementation intricacy. These inefficiencies hinder the scalability and feasibility of quantum multipliers in high-performance computing applications. A proposed solution to these issues is to introduce a cost-effective, parity-preserving reversible quantum block synthesized through an established method that produces a network list of multi-controlled Toffoli (MCT) gates. This Toffoli-based network is then optimized using various techniques, ultimately transforming it into a network of fundamental quantum gates. This approach decreases quantum expenses, eliminates unnecessary outputs, and enhances quantum gate efficiency. Integrating this innovative technique into the reversible quantum Vedic multipliers offers a more efficient, cost-effective, and scalable solution than current approaches. All proposed designs, such as a half adder-subtractor, a ripple carry adder (RCA), and two-bit and four-bit Vedic multipliers, are suggested based on functional blocks and pre-existing components. The suggested structures undergo evaluation in comparison to existing state-of-the-art procedures, demonstrating their cost-effectiveness. The observed average savings for two-bit and four-bit Vedic multipliers, with respect to QC, number of CNOT-V/V+ count, GO, CI, and GC, are 20.01%, 19.38%, 37.51%, 37.51%, and 54.89%, and 22.71%, 18.78%, 27.23%, 31.10%, and 42.38%, respectively when compared to previous studies. Furthermore, all suggested circuits are evaluated and confirmed using the IBM quantum laboratory.
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit. Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,
Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology.When building quantum computers, for example, the use of reversible logic is unavoidable.The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit.The multiplication operation is regarded as one of the most crucial in the ALU unit.In this paper, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits.The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic.The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.
At present days , reversible logic circuits have many applications in the field of optical information processing, digital signal processing , nano technology and quantum computing . Reversible logic plays an important role when computations with minimum energy dissipation are considered. The purpose of designing reversible logic is to decrease the number of area, power, garbage outputs , constant inputs, quantum cost, reversible gates, delay and hardware complexity . This paper reveals a review on some reversible logic gates, which is useful in designing more complex systems having reversible circuits and can do execution of more complex operations using quantum computers. In upcoming days digital technology will be using reversible logic gates in order to reduce the propagation delay and power consumption as it provides negligible loss of information in the circuit. Keywords: Reversible Gate, Garbage output, quantum cost, Reversible logic, Power dissipation