Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions
Bodhisatwa Sadhu, Kevin Tien, Sudipto Chakraborty, David Frank, Pat Rosno, Daniel Moertl, Mark Yeck, John F. Bulzacchelli, D. Frolov, Devin Underwood, Ken Inoue, Christian W. Baks, Daniel Ramirez, Jeremy T. Ekman, Ryan Black, Timothy J. Schmerbeck, Ray Richetta, Dereje Yilma, Andrew Davies, Joseph Glick, Dorothy Wisnieff, Bryce Snell, John Timmerwilke, R. P. Robertazzi, George Zettles, Scott Lekuch, Scott M. Willenborg, B. Gaucher, Daniel Friedman
Quantum computers offer the promise of accelerated solutions for types of problems that are computationally unaffordable or intractable for classical computers, such as the simulation of quantum mechanics itself, quantum chemistry, and mathematical challenges like factoring large numbers. However, the relatively high error rate per quantum computing operation in the systems of today and of those expected to be developed in the future remains a key obstacle. To address this challenge, quantum error correction (QEC), which enables the creation of error-corrected (logical) qubits from a collection of physical qubits, is required. Depending on the choice of QEC code, hundreds of physical qubits may be required to implement a single logical qubit. As a result, the race to the creation of quantum computing systems capable of outperforming classical computing systems is largely a race to create quantum computers at the scale needed to support QEC. The criticality of scaling is evident in the quantum computing roadmaps produced by major research labs in this field, such as the one from IBM shown in Fig. 1. Starting from systems with only a few physical qubits a few years ago, the roadmap projects quantum computers with around 100,000 physical qubits and thousands of logical qubits by 2033 or so.
Quantum computers offer the promise of accelerated solutions for types of problems that are computationally unaffordable or intractable for classical computers, such as the simulation of quantum mechanics itself, quantum chemistry, and mathematical challenges like factoring large numbers. However, the relatively high error rate per quantum computing operation in the systems of today and of those expected to be developed in the future remains a key obstacle. To address this challenge, quantum error correction (QEC), which enables the creation of error-corrected (logical) qubits from a collection of physical qubits, is required. Depending on the choice of QEC code, hundreds of physical qubits may be required to implement a single logical qubit. As a result, the race to the creation of quantum computing systems capable of outperforming classical computing systems is largely a race to create quantum computers at the scale needed to support QEC. The criticality of scaling is evident in the quantum computing roadmaps produced by major research labs in this field, such as the one from IBM shown in Fig. 1. Starting from systems with only a few physical qubits a few years ago, the roadmap projects quantum computers with around 100,000 physical qubits and thousands of logical qubits by 2033 or so.
Quantum computing holds the potential to solve problems beyond the capabilities of classical computers. However, realizing practical large-scale quantum computers faces critical challenges, including the key bottleneck in wiring quantum processors operating at cryogenic temperatures to their room temperature control electronics. This article explores cryo-CMOS ICs as an enabling technology to circumvent such a wiring bottleneck. After reviewing the basics of quantum computing and the behavior of CMOS devices at cryogenic temperatures, the requirements for the interface electronics for superconducting and semiconductor qubits are discussed, and state-of-the-art cryo-CMOS circuit solutions are briefly described, including a few hints to other qubit platforms. Finally, the article concludes with an overview of future challenges to be addressed to realize the vision of cryo-CMOS technology as an enabler of large-scale quantum computers with practical applications.
Quantum computers hold the promise to solve some of the most complex problems of today. The core of a quantum computer is a quantum processor, which is composed of quantum bits (qubits). Qubits are fragile and their state needs to be corrected in real time by a classical controller. Today, the control of qubits is done at room temperature by racks of instruments, while qubits operate at several tens of milli-Kelvin. To ensure compactness, and eventually scalability, we have proposed the use of controllers operating at a few Kelvin, so as to reduce the length of control cables, while potentially enabling superconductive interconnects, which enable virtually zero resistance and low thermal conductivity. We have chosen CMOS to achieve this functionality due to its scalable nature and overall miniaturization opportunities. Cryogenic CMOS, or cryo-CMOS, circuits and systems need to be carefully designed, so as to ensure low noise and high bandwidth, while operating at strict power budgets of a few milliwatts per qubit. In this paper, we outline the requirements of a classical controller and we show examples of such circuits and systems. Results and perspectives are presented discussing a roadmap for the future.
Quantum computers hold the promise to solve some of the most complex problems of today. The core of a quantum computer is a quantum processor, which is composed of quantum bits (qubits). Qubits are fragile and their state needs to be corrected in real time by a classical controller. Today, the control of qubits is done at room temperature by racks of instruments, while qubits operate at several tens of milli-Kelvin. To ensure compactness, and eventually scalability, we have proposed the use of controllers operating at a few Kelvin, so as to reduce the length of control cables, while potentially enabling superconductive interconnects, which enable virtually zero resistance and low thermal conductivity. We have chosen CMOS to achieve this functionality due to its scalable nature and overall miniaturization opportunities. Cryogenic CMOS, or cryo-CMOS, circuits and systems need to be carefully designed, so as to ensure low noise and high bandwidth, while operating at strict power budgets of a few milliwatts per qubit. In this paper, we outline the requirements of a classical controller and we show examples of such circuits and systems. Results and perspectives are presented discussing a roadmap for the future.
Quantum computing holds the promise to achieve unprecedented computation power and to solve problems today intractable. State-of-the-art quantum processors consist of arrays of quantum bits (qubits) operating at a very low base temperature, typically a few tens of mK, as shown in Fig. 15.5.1 The qubit states degrade naturally after a certain time, upon loss of quantum coherence. For proper operation, an error-correcting loop must be implemented by a classical controller, which, in addition of handling execution of a quantum algorithm, reads the qubit state and performs the required corrections. However, while few qubits (~10) in today's quantum processors can be easily connected to a room-temperature controller, it appears extremely challenging, if not impossible, to manage the thousands of qubits required in practical quantum algorithms [1].
This review article provides a comprehensive overview of recent developments in the field of quantum error correction (QEC), which stands as one of the biggest challenges for quantum computing. The extreme sensitivity of quantum systems to environmental noise makes it difficult to build reliable and scalable quantum computers. Inspired by pioneering codes like those from Shor and Steane, this work discusses the most promising QEC approaches today, particularly topological codes such as surface codes and low-density parity-check (LDPC) codes. The paper delves into critical experimental successes from industry leaders like Google, IBM, and Quantinuum, including their ”below-threshold” error correction demonstrations and roadmaps for fault-tolerant systems. It also presents a comparative analysis between classical algorithms like Minimum-Weight Perfect Matching (MWPM) and newer, machine learning-based decoder approaches. The discussion section addresses open problems that need to be solved in the future, such as correlated noise, cryogenic control, and the creation of fault-tolerant logical gate sets. This review aims to summarize the current state of the QEC field, serving as a guiding resource for both academics and industry professionals in shaping future research and development strategies.
This review article provides a comprehensive overview of recent developments in the field of quantum error correction (QEC), which stands as one of the biggest challenges for quantum computing. The extreme sensitivity of quantum systems to environmental noise makes it difficult to build reliable and scalable quantum computers. Inspired by pioneering codes like those from Shor and Steane, this work discusses the most promising QEC approaches today, particularly topological codes such as surface codes and low-density parity-check (LDPC) codes. The paper delves into critical experimental successes from industry leaders like Google, IBM, and Quantinuum, including their ”below-threshold” error correction demonstrations and roadmaps for fault-tolerant systems. It also presents a comparative analysis between classical algorithms like Minimum-Weight Perfect Matching (MWPM) and newer, machine learning-based decoder approaches. The discussion section addresses open problems that need to be solved in the future, such as correlated noise, cryogenic control, and the creation of fault-tolerant logical gate sets. This review aims to summarize the current state of the QEC field, serving as a guiding resource for both academics and industry professionals in shaping future research and development strategies.