Quantum computing promises to solve complex problems beyond the capabilities of classical computers. However, the practical implementation of quantum algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices is significantly challenged by various noise sources that degrade computational fidelity. Transpilation—the process of converting high-level quantum circuits into optimized, hardware-specific instructions—plays a crucial role in mitigating these noise effects. In this paper, we present a comprehensive study on enhancing noise resilience in quantum algorithms through advanced transpilation techniques, evaluated using the SupermarQ benchmarking suite. By systematically analyzing the impact of different optimization levels in Qiskit’s transpiler on a diverse set of quantum algorithms, we demonstrate how specific transpilation strategies influence key performance metrics related to noise resilience. Our results show that higher optimization levels can improve metrics such as Liveness (LV) and Parallelism (PL), leading to more reliable quantum computations on NISQ hardware. This work contributes to the development of noise-adaptive transpilation methods that incorporate noise characteristics into the optimization process, ultimately enhancing the practical viability of quantum algorithms.
Quantum computing promises to solve complex problems beyond the capabilities of classical computers. However, the practical implementation of quantum algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices is significantly challenged by various noise sources that degrade computational fidelity. Transpilation—the process of converting high-level quantum circuits into optimized, hardware-specific instructions—plays a crucial role in mitigating these noise effects. In this paper, we present a comprehensive study on enhancing noise resilience in quantum algorithms through advanced transpilation techniques, evaluated using the SupermarQ benchmarking suite. By systematically analyzing the impact of different optimization levels in Qiskit’s transpiler on a diverse set of quantum algorithms, we demonstrate how specific transpilation strategies influence key performance metrics related to noise resilience. Our results show that higher optimization levels can improve metrics such as Liveness (LV) and Parallelism (PL), leading to more reliable quantum computations on NISQ hardware. This work contributes to the development of noise-adaptive transpilation methods that incorporate noise characteristics into the optimization process, ultimately enhancing the practical viability of quantum algorithms.
The benchmark of Noisy Intermediate-Scale Quantum (NISQ) computers plays a major role in the research and development of quantum devices and algorithms. Our study aims to investigate a single metric of benchmarking for the Noisy Intermediate-Scale Quantum device. We use state-of-the-art applications to generate a device-score according to our proposed formula. Our study utilizes Quantum Volume (QV) to determine the qubit circuit size for each device. Furthermore, we utilize SupermarQ to determine each application's benchmark score, utilizing their 5 feature vectors to indicate the circuit performance, and applying their circuit optimization techniques to configure the transpiler. Our experiment shows that device-score of the simulated IBM backend are directly correlated to Quantum Volume. However, it should be noted that topology and gate error are also embedded in the benchmark scores of the applications. Because of this, our study introduces the device-score, a single number metric that provides a more precise scale with the assistance of Quantum Volume and SupermarQ.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
Noise in current quantum hardware (NISQ devices) poses a major obstacle by degrading gate operations and overall circuit fidelity toward FTQC. Traditional quantum error correction (QEC) is effective but resource-intensive, requiring several extra qubits and operations beyond the reach of near-term devices. Quantum error mitigation (QEM) offers a complementary path by reducing the impact of error prior to full correction. We present an adaptive pulse-level QEM using genetic algorithms to dynamically adjust control pulses in real-time, improving algorithm fidelity without modifying the logic structure of a quantum circuit. By targeting pulse parameters directly, this method reduces the impact of various noise sources, improving algorithm resilience in quantum circuits. To demonstrate the effectiveness of our methodology, we apply our protocol to five key quantum algorithms, including Bernstein-Vazirani, DeutschJozsa, Grover's search, Quantum Fourier Transform (QFT), and its inverse (IQFT). Experimental results show that our pulse-level optimization strategy provides a flexible and efficient solution for increasing fidelity during the noisy execution of quantum circuits. Our work contributes to advance error mitigation techniques, essential for robust quantum computing, which will increasingly require HPC infrastructure as quantum systems scale.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
Abstract Noisy Intermediate-Scale Quantum (NISQ) devices are near-term quantum computing devices that inherently suffer from imperfect gate implementation, decoherence, and measurement noise. The main type of variational quantum algorithms(VQAs) is based on Parameterized Quantum Circuits (PQCs), which, however, face practical challenges due to optimization instability of optimization caused by noise and reduced performance. In this paper, we suggest a comprehensive noise-resilient optimization framework for PQCs, which explicitly incorporates noise-resilient circuit architecture design, incorporating noise-aware training strategies into the variational optimization loop. The framework uses circuit structures that are efficient in depth and are hardware compatible in addition to adaptive optimizer choice, stochastic optimization, and averaging as a part of repeated measurement to reduce the impacts of realistic noise. Large-scale experiments are performed with different amounts of qubits, depths of the circuit and noise strengths with realistic noise models. The findings indicate that the convergence rate is faster, the stability is increased, the variability of run-to-run variability is minimized, and other robustness is better than the noise-unaware optimization techniques. Moreover, systematic studies determine optimal operating regions that optimally trade-off expressibility and noise tolerance to offer useful design advice on trusted implementation of VQAs with near-term quantum hardware.