Quantum circuits for multiplication are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant implementations. The costs of implementing T and double-qubit gates are higher than those of other one-qubit gates in the Clifford + T group. In addition, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. Therefore, we reduce T and CNOT gates and circuit width as the primary optimization goal in this paper. We propose an algorithm for multiplication with two unchanged operands. Preserving both operands of the multiplication is important for realizing some quantum algorithms, such as quantum bilinear interpolation. Using this algorithm, we design the circuit of the integer multiplier with two unchanged operands reducing CNOT gates. Next, we develop a Clifford + T circuit for the multiplier and introduce new optimization rules to reduce T gates. Comparative analysis shows that the proposed multiplier achieves the best width among existing multipliers. Compared to multipliers with two unchanged operands that use at most one ancillary qubit, our proposed multiplier has the best T-count, T-depth, and CNOT-count.
Quantum circuits for multiplication are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant implementations. The costs of implementing T and double-qubit gates are higher than those of other one-qubit gates in the Clifford + T group. In addition, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. Therefore, we reduce T and CNOT gates and circuit width as the primary optimization goal in this paper. We propose an algorithm for multiplication with two unchanged operands. Preserving both operands of the multiplication is important for realizing some quantum algorithms, such as quantum bilinear interpolation. Using this algorithm, we design the circuit of the integer multiplier with two unchanged operands reducing CNOT gates. Next, we develop a Clifford + T circuit for the multiplier and introduce new optimization rules to reduce T gates. Comparative analysis shows that the proposed multiplier achieves the best width among existing multipliers. Compared to multipliers with two unchanged operands that use at most one ancillary qubit, our proposed multiplier has the best T-count, T-depth, and CNOT-count.
Abstract Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. But neglecting the cost of CNOT gates may lead to a significant underestimation. Moreover, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. As a result, reducing T-count, T-depth, CNOT-count, CNOT-depth, and circuit width has become the important optimization goal. We use 3-bit Hermitian gates to design basic arithmetic operations. Then, we present a special multiplier and a divider using basic arithmetic operations, where 'special' means that one of the two operands of multiplication is non-zero. Next, we use new rules to optimize the Clifford + T circuits of the special multiplier and divider in terms of T-count, T-depth, CNOT-count, CNOT-depth, and circuit width. Comparative analysis shows that the proposed multiplier and divider have lower T-count, T-depth, CNOT-count, and CNOT-depth than the current works. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the best current work. Further, the circuit widths of the proposed n-bit multiplier and divider are 3n. I.e., our multiplier and divider reach the minimum width of multipliers and dividers, keeping an operand unchanged.
Arithmetic operations are an important component of many quantum algorithms. Optimizing quantum circuits for these operations therefore leads to more efficient implementations of the corresponding algorithms. In this paper, we develop new fault-tolerant quantum circuits for various integer division algorithms (both reversible and non-reversible). These circuits, when implemented in the Clifford+T gate set, achieve improvements in the asymptotic T-count and CNOT-count from O(n2) to O(nm), and in the asymptotic T-depth from O(n2) to O(nlogm), where n and m are the bit lengths of the dividend and divisor, respectively. The qubit counts are significantly lower than those in previous works. We achieve this through careful modifications of the division algorithms and by expressing them in terms of a primitive we call COMP-N-SUB that compares two integers and conditionally subtracts them. We show that this primitive can be implemented at a cost, in terms of both Clifford and non-Clifford gates, comparable to that of one addition. By contrast, performing comparison and conditional subtraction separately would cost roughly as much as a controlled addition plus a regular addition.
Quantum circuits performing arithmetic operations are critical in quantum computing because of the need for such operations in proven quantum algorithms. Although quantum computers are becoming increasingly resourceful, the number of qubits currently available is still limited. Furthermore, these qubits are heavily affected by internal and external noise. It has been proven that quantum circuits built using Clifford +T gates can be made fault tolerant. However, the use of the T gates comes at a very high cost. If the number of T gates used in a circuit is not optimized, the cost of the circuit will be increased excessively. As a consequence, it is essential to optimize the circuits so that they are as resource efficient as possible and also noise tolerant. This paper presents the design of a circuit to perform the multiplication of two integers. The circuit is built using only Clifford +T gates for compatibility with error detection and correction codes. It outperforms the circuits in the state of the art in terms of T count and T depth.
Abstract Current quantum computers have a limited number of resources and are heavily affected by internal and external noise. Therefore, small, noise-tolerant circuits are of great interest. With regard to circuit size, it is especially important to reduce the number of required qubits. Concerning to fault-tolerance, circuits entirely built with Clifford+T gates allow the use of error correction codes. However, the T-gate has an excessive cost, so circuits with a high number of T-gates should be avoided. This work focuses on optimising in such terms an operation that is widely used in larger circuits and algorithms: the calculation of the absolute-value of two’s complement encoded integers. The proposed circuit halves the number of required T gates with respect to the best circuit currently available in the literature. Moreover, our circuit requires at least 2 qubits less than the other circuits for such an operation.
Although with some yet severe limitations, Physical working Quantum Computers are becoming available for end users. Such devices are based on the rules of Quantum Mechanics, which state that physical systems evolve through unitary transformations. However, as in the classical case, in order to have a model of computation, such unitary evolutions are expressed/approximated inside Quantum Computers in terms of a finite set of one/two qubit operations (i.e., through a universal set of gates). Single qubit gates are fault-tolerant, while the same cannot be said for two qubit gates. Hence, unitary matrices adopted in Quantum Algorithms must be synthesized in terms of this universal set of operations to obtain a quantum circuit. In such synthesis procedure we prefer circuits with minimum number of qubits and with minimum circuit depth. Clifford+T universal set is one of the most adopted in the literature for synthesis. In such set we have 3 single qubit gates and the CNOT, which is a two qubit gate. Many efforts have been directed to devise algorithms that synthesize general unitary matrices into Clifford+T circuits. These algorithms usually tend to optimize circuit depth or eventually the number of T gates. Since two qubit gates are not fault tolerant, in this work we propose an ASP based technique to minimize the number of CNOT gates inside a Clifford+T circuit. Moreover, in real world quantum computers, qubit are usually connected to each other according to some particular topology, thus providing further constraints. Two qubit gates —hence, CNOT gate— can be directly applied only to pair of gates that are connected. Such constraint has to be taken into account during the synthesis of CNOT minimal circuits. We propose an ASP model to solve the problem of synthesizing CNOT minimal circuits under topological constraints. We provide experimental evidence of the scalability of our proposal.
In the last year, physical working Quantum Computers have been built and made available for the end users. Such devices, working under the rules of Quantum Mechanics, can only apply a finite set of one/two qubit operations that form a universal set of gates. Single qubit gates are fault-tolerant, while the same cannot be said for two qubit gates. Hence, unitary matrices adopted in Quantum Algorithms must be synthesized in terms of this universal set of operations to obtain a quantum circuit. This synthesis procedure, however, is not constraint-free. In fact, we prefer circuits with minimum number of qubits and with minimum circuit depth. Clifford+T universal set is one of the most adopted in the literature for synthesis. In such set we have 3 single qubit gates and the CNOT, which is a two qubit gate. Many efforts have been directed to devise algorithms that synthesize general unitary matrices into Clifford+T circuits. These algorithms usually tend to optimize circuit depth or eventually the number of T gates. Since two qubit gates are not fault tolerant, in this work we propose an ASP based technique to minimize the number of CNOT gates inside a Clifford+T circuit. We start from a SAT encoding of the problem, and we translate it into an ASP model over a graph, by first working with a generic graph, and then by adopting the structure of a layered DAG. We provide experimental evidence of the scalability of our proposal.