Quantum Hardware I: Ion Trap Qubits

Bernard Zygelman

Prakash Murali, Dripto M. Debroy, Kenneth R. Brown +1 more

Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements.Towards realizing QCCD-based TI systems with 50-100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. To enable our study, we built a design toolflow which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near-future and accelerate the progress towards practical QC systems.

Christopher J. Ballance

Austin S. Adams, Elton Pinto, Jeffrey Young +4 more

Ion trap quantum hardware promises to provide a computational advantage over classical computing for specific problem spaces while also providing an alternative hardware implementation path to cryogenic quantum systems as typified by IBM's quantum hardware. However, programming ion trap systems currently requires both strategies to mitigate high levels of noise and also tools to ease the challenge of programming these systems with pulse- or gate-level operations. This work focuses on improving the state-of-the-art for quantum programming of ion trap testbeds through the use of a quantum language specification, QCOR, and by demonstrating multi-level optimizations at the language, intermediate representation, and hardware backend levels. We implement a new QCOR/XACC backend to target a general ion trap testbed and then demonstrate the usage of multi-level optimizations to improve circuit fidelity and to reduce gate count. These techniques include the usage of a backend-specific numerical optimizer and physical gate optimizations to minimize the number of native instructions sent to the hardware. We evaluate our compiler backend using several QCOR benchmark programs, finding that on present testbed hardware, our compiler backend maintains the number of two-qubit native operations but decreases the number of single-qubit native operations by 1.54 times compared to the previous compiler regime. For projected testbed hardware upgrades, our compiler sees a reduction in two-qubit native operations by 2.40 times and one-qubit native operations by 6.13 times.

Grzegorz H. Kasprowicz

Kenneth R. Brown, Jungsang Kim, Christopher R. Monroe

Abstract The first generation of quantum computers are on the horizon, fabricated from quantum hardware platforms that may soon be able to tackle certain tasks that cannot be performed or modelled with conventional computers. These quantum devices will not likely be universal or fully programmable, but special-purpose processors whose hardware will be tightly co-designed with particular target applications. Trapped atomic ions are a leading platform for first-generation quantum computers, but they are also fundamentally scalable to more powerful general purpose devices in future generations. This is because trapped ion qubits are atomic clock standards that can be made identical to a part in 1015, and their quantum circuit connectivity can be reconfigured through the use of external fields, without modifying the arrangement or architecture of the qubits themselves. In this forward-looking overview, we show how a modular quantum computer with thousands or more qubits can be engineered from ion crystals, and how the linkage between ion trap qubits might be tailored to a variety of applications and quantum-computing protocols.