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Heterogeneous Integration of Spin-photon Interfaces with a Scalable CMOS Platform

Linsen Li, Lorenzo De Santis, Isaac Harris, Kevin C. Chen, Ian Christen, Matthew E. Trusheim, Ruonan Han, Dirk Englund

Published Jan 1, 2024• 2 citations
Publisher

Abstract

We introduce a quantum system-on-chip (QSoC) architecture based on (I) a co-designed diamond quantum memory array, (II) a custom CMOS backplane, and (III) a protocol for fully connected cluster state generation.
DOI
10.1364/cleo_fs.2024.fw3k.2

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Color centers in diamonds have emerged as a leading solid-state platform for advancing quantum technologies, satisfying the DiVincenzo criteria and recently achieving a quantum advantage in secret key distribution. Recent theoretical works estimate that general-purpose quantum computing using local quantum communication networks will require millions of physical qubits to encode thousands of logical qubits, which presents a substantial challenge to the hardware architecture at this scale. To address the unanswered scaling problem, in this work, we first introduce a scalable hardware modular architecture "Quantum System-on-Chip" (QSoC) that features compact two-dimensional arrays "quantum microchiplets" (QMCs) containing tin-vacancy (SnV-) spin qubits integrated on a cryogenic application-specific integrated circuit (ASIC). We demonstrate crucial architectural subcomponents, including (1) QSoC fabrication via a lock-and-release method for large-scale heterogeneous integration; (2) a high-throughput calibration of the QSoC for spin qubit spectral inhomogenous registration; (3) spin qubit spectral tuning functionality for inhomogenous compensation; (4) efficient spin-state preparation and measurement for improved spin and optical properties. QSoC architecture supports full connectivity for quantum memory arrays in a set of different resonant frequencies and offers the possibility for further scaling the number of solid-state physical qubits via larger and denser QMC arrays and optical frequency multiplexing networking.