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IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum

An Accurate Union Find Decoder for Quantum Error Correction on the Toric Code

Federico Valentino, Beatrice Branchini, Davide Conficconi, Donatella Sciuto, Marco Domenico Santambrogio

Published May 27, 2024• 3 citations
Publisher

Abstract

Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. One main limiting factor is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations. Within this context, hardware accelerators, such as FPGAs, represent a valuable approach to fulfilling the QEC requirements. Nevertheless, the literature falls short in proposing solutions optimized for the toric code, which is capable of encoding two logical qubits and, therefore, requires fewer qubits to correct errors. This manuscript presents QUEKUF, an FPGA-based QEC dataflow architecture dealing with toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC that a centralized controller orches-trates for data movement and operation decisions. Experimental results show that our design attains up to 20.14 × improvement in execution time over a C++ implementation while keeping a high accuracy, similar to the theoretical framework.

DOI
10.1109/ipdpsw63119.2024.00032

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Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. The main limiting factor for quantum devices is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations to real-life-sized problems. Within this context, hardware accelerators, such as Field Programmable Gate Arrays (FPGAs), represent a valuable approach to fulfilling QEC requirements. Nevertheless, the literature falls short in proposing solutions targeting the toric code, a type of quantum Low-Density Parity Check code capable of encoding two logical qubits, thus requiring fewer physical qubits. This manuscript presents QUEKUF , an FPGA-based QEC dataflow architecture dealing with the toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC, which a centralized controller orchestrates for data movement and operation decisions. We also provide a latency-oriented resource optimization model to identify the best theoretical configuration of QUEKUF that minimizes latency and optimizes resource requirements based upon high-level quantum parameters. Experimental results show that QUEKUF attains up to \(7.30\times\) speedup and \(81.51\times\) improvement in energy efficiency over a C++ implementation with error-free syndromes while keeping high accuracy.

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Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. One main limiting factor is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations. Within this context, hardware accelerators, such as FPGAs, represent a valuable approach to fulfilling the QEC requirements. Nevertheless, the literature falls short in proposing solutions optimized for the toric code, which is capable of encoding two logical qubits and, therefore, requires fewer qubits to correct errors. This manuscript presents QUEKUF, an FPGA-based QEC dataflow architecture dealing with toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC that a centralized controller orches-trates for data movement and operation decisions. Experimental results show that our design attains up to 20.14 × improvement in execution time over a C++ implementation while keeping a high accuracy, similar to the theoretical framework.
Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. The main limiting factor for quantum devices is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations to real-life-sized problems. Within this context, hardware accelerators, such as Field Programmable Gate Arrays (FPGAs), represent a valuable approach to fulfilling QEC requirements. Nevertheless, the literature falls short in proposing solutions targeting the toric code, a type of quantum Low-Density Parity Check code capable of encoding two logical qubits, thus requiring fewer physical qubits. This manuscript presents QUEKUF , an FPGA-based QEC dataflow architecture dealing with the toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC, which a centralized controller orchestrates for data movement and operation decisions. We also provide a latency-oriented resource optimization model to identify the best theoretical configuration of QUEKUF that minimizes latency and optimizes resource requirements based upon high-level quantum parameters. Experimental results show that QUEKUF attains up to 7.30×7.30\times7.30× speedup and 81.51×81.51\times81.51× improvement in energy efficiency over a C++ implementation with error-free syndromes while keeping high accuracy.
Quantum computation promises significant computational advantages over classical computation for some problems. However, quantum hardware suffers from much higher error rates than in classical hardware. As a result, extensive quantum error correction is required to execute a useful quantum algorithm. The decoder is a key component of the error correction scheme whose role is to identify errors faster than they accumulate in the quantum computer and that must be implemented with minimum hardware resources in order to scale to the regime of practical applications. In this work, we consider surface code error correction, which is the most popular family of error correcting codes for quantum computing, and we design a decoder micro-architecture for the Union-Find decoding algorithm. We propose a three-stage fully pipelined hardware implementation of the decoder that significantly speeds up the decoder. Then, we optimize the amount of decoding hardware required to perform error correction simultaneously over all the logical qubits of the quantum computer. By sharing resources between logical qubits, we obtain a 67% reduction of the number of hardware units and the memory capacity is reduced by 70%. Moreover, we reduce the bandwidth required for the decoding process by a factor at least 30x using low-overhead compression algorithms. Finally, we provide numerical evidence that our optimized micro-architecture can be executed fast enough to correct errors in a quantum computer.
Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
Reliable large-scale quantum computation relies on fault-tolerant architectures, where quantum error correction (QEC) continuously extracts and decodes error syndromes in real time. A critical component in QEC is the decoder, a classical subsystem that must simultaneously deliver high logical accuracy and ultra-low latency. This paper presents a novel algorithm-hardware co-design that improves the accuracy-latency trade-off over existing approaches such as vanilla Minimum-Weight Perfect Matching (MWPM) and Union-Find (UF) decoders. At the algorithmic level, we introduce coset ensemble decoding, which improves UF decoding by explicitly exploiting logically equivalent cosets. Our method performs ensemble forest exploration to generate multiple coset-consistent candidates and aggregates them to approximate coset-level maximum-likelihood decoding. We further reduce computational and memory complexity via reverse-order elimination and lossless graph compression, without sacrificing accuracy. At the hardware level, we design a domain-specific architecture that temporally reuses resources, avoiding the code-distance-proportional resource growth in prior spatial architectures. Several optimizations, such as multi-bank memory hashing and hierarchical ID mapping, are proposed to mitigate pipeline stalls and memory conflicts under highly concurrent access patterns. Under a circuit-level depolarizing noise model, our co-design approach achieves a better accuracy-latency trade-off than prior MWPM- and UF-based decoders, while reducing FPGA LUT consumption by up to 8.2 times compared with reported UF-based decoder resources. The tunable candidate number further exposes a flexible design knob, enabling users to tailor decoding performance to the requirements of different fault-tolerant workloads. Our implementation is publicly available at https://github.com/IMSeonL/coset-ensemble-decoder.
Quantum Error Correction is an essential key ingredient for large-scale Quantum Computing devices. Indeed, a fast, scalable, and accurate decoding and correction process of errors appearing in qubits is critical to guarantee fault tolerance and usability. In this context, the Union-Find decoder incarnates a promising approach for such an essential task, as proved by various literature studies. Nonetheless, further advancements in this area are still feasible. For this reason, we propose a Systolic Array-based architecture for the Union-Find decoder that exploits a novel communication and decoding scheme to speed up the overall process. Furthermore, we design three solutions based on such a scheme and evaluate them according to different metrics, such as latency and accuracy.
Current generation of Noisy Intermediate-Scale Quantum devices is mainly limited by noise, thus making Quantum Error Correction (QEC) mechanisms of paramount importance. QEC is carried out through classical computing architectures, and Field Programmable Gate Arrays (FPGAs) represent a promising platform on which deploying decoding algorithms. Nevertheless, accelerating QEC with FPGAs is a largely unexplored topic in the State of the Art, making it urgent to clearly define the requirements that these designs must satisfy. For this reason, in this work, we analyze literature solutions for FPGA-based QEC and identify the mandatory Key Performance Indicators (KPIs) to address when developing FPGA designs for this task. These KPIs are crucial to guide future research and unleash the full computing power of quantum devices.