As Quantum Computers continue to increase in size, throughput has not increased proportionally [1]. Errors in qubit measurement and gate operations continue to increase with circuit width and depth. In order to maximize machine throughput, researchers have begun exploring ways of parallelizing circuit execution [2]–[9]. Due to the noisyness of quantum computers, this requires new algorithms for efficient resource allocation, qubit mapping, and scheduling. We improve on existing greedy algorithms by formulating the mapping search as a Binary Integer Non-Linear Programming (BINLP) problem. We model practical constraints and propose new heuristics for determining the goodness of a mapping. We evaluate our mappings on several sets of benchmark circuits and investigate the usefulness of parallel execution for circuit cutting, QAOAs, and deep circuits. We observe similar fidelity compared to Qiskit's transpiler for circuit cutting and throughput benchmarks. We observe greater fidelity over Qiskit's transpiler for dense QAOA ansatzes. Finally, we find that parallel circuit cutting provides greater fidelity than full-circuit execution.
As Quantum Computers continue to increase in size, throughput has not increased proportionally [1]. Errors in qubit measurement and gate operations continue to increase with circuit width and depth. In order to maximize machine throughput, researchers have begun exploring ways of parallelizing circuit execution [2]–[9]. Due to the noisyness of quantum computers, this requires new algorithms for efficient resource allocation, qubit mapping, and scheduling. We improve on existing greedy algorithms by formulating the mapping search as a Binary Integer Non-Linear Programming (BINLP) problem. We model practical constraints and propose new heuristics for determining the goodness of a mapping. We evaluate our mappings on several sets of benchmark circuits and investigate the usefulness of parallel execution for circuit cutting, QAOAs, and deep circuits. We observe similar fidelity compared to Qiskit's transpiler for circuit cutting and throughput benchmarks. We observe greater fidelity over Qiskit's transpiler for dense QAOA ansatzes. Finally, we find that parallel circuit cutting provides greater fidelity than full-circuit execution.
We consider the problem of mapping a logical quantum circuit onto a given hardware with limited 2-qubit connectivity. We model this problem as an integer linear program, using a network flow formulation with binary variables that includes the initial allocation of qubits and their routing. We consider several cost functions: an approximation of the fidelity of the circuit, its total depth, and a measure of cross-talk, all of which can be incorporated in the model. Numerical experiments on synthetic data and different hardware topologies indicate that the error rate and depth can be optimized simultaneously without significant loss. We test our algorithm on a large number of quantum volume circuits, optimizing for error rate and depth; our algorithm significantly reduces the number of CNOTs compared to Qiskit’s default transpiler SABRE [ 19 ] and produces circuits that, when executed on hardware, exhibit higher fidelity.
Noisy intermediate-scale quantum (NISQ) devices with limited qubit count and connectivity limit the scale of quantum circuits that can be executed. Circuit cutting methods simulate larger quantum computers by decomposing large circuits into small subcircuits that can be executed on NISQ hardware. Existing circuit cutting methods only consider the qubit count of the target hardware for finding the locations of cuts on the circuits. This can result in deeper subcircuits after mapping on the hardware. Fidelity decays exponentially with circuit depth and diminishes the quality of execution. We propose a circuit-cutting framework that reduces variance in the depth of subcircuits after mapping to the hardware. Our method formulates the initial circuit cutting as a multi-objective optimization problem based on an evolutionary search method with the number of cuts and the maximum depth of individual routed subcircuits as fitness objectives. This method is implemented as an extension to the existing Qiskit Circuit Cutting Addon, which allows for integration in existing flows. Our approach achieves reductions in routed subcircuit depth of up to 9.9% across benchmark circuits compared with baseline methods.
Optimizing and simulating quantum circuits at scale are critical bottlenecks in realizing the full potential of quantum computing. This thesis delivers a comprehensive suite of systems to overcome these limitations, spanning both physical compilation and classical simulation. For quantum circuit optimization, we first automate the discovery and verification of transformation rules by introducing Equivalence Circuit Class (ECC) sets and an efficient generation algorithm for arbitrary gate sets. We deploy these rules within the superoptimizer Quartz, which utilizes a cost-based backtracking search to escape local minima that trap traditional rule-based methods. To eliminate the exponential runtime penalties inherent to pure search, we introduce QALM, a hybrid optimization framework. By unifying search-based exploration with greedy rule-based exploitation in an interleaved control loop, QALM dynamically escapes local minima without exhaustive backtracking. Evaluated across a large benchmark suite of 248 diverse circuits, QALM outperforms existing search-based optimizers in final circuit quality while operating with the computational efficiency of rule-based systems. While the prior two approaches aim for global optimization, this problem is intrinsically QMA-hard, creating a bottleneck for large programs. To circumvent this issue and scale up, we introduce OAC, a cut-and-meld circuit optimization algorithm. OAC cuts a circuit into subcircuits, applies an existing oracle optimizer independently, and seamlessly melds the results. This algorithm operates with a linear number of oracle calls while attaining local optimality. Empirical evaluation shows that OAC significantly improves the efficiency of state-of-the-art optimizers while enhancing overall quality. Beyond physical execution, the scalable simulation of quantum circuits on classical hardware presents another major challenge. To address this, we present Atlas, a distributed GPU-based simulator that hierarchically partitions circuits to exploit data parallelism while minimizing communication overhead. By leveraging integer linear programming to allocate structurally related gates to nearby GPUs and dynamic programming for kernel scheduling, Atlas runs significantly faster than prior state-of-the-art GPU simulators. Together, these frameworks provide a robust toolchain, improving both the execution of quantum circuits on physical devices and their scalable classical simulation.
Neutral atom quantum computers (NAQC) are emerging as a promising, scalable quantum computing platform because of their long qubit coherence, flexible qubit arrangement, and multiqubit gate capabilities. However, circuit execution often requires physically moving qubits, making compilation a critical optimization challenge. We propose a circuit independent mathematical framework built on graph-theoretic combinatorial optimization that determines the minimal number of required qubit transfers. This model captures spatial constraints specific to NAQC platforms with zone-limited gate operations and multi-qubit gates. From this framework, we encode the qubit mapping problem as a nonlinear integer program and solve it using a genetic algorithm, enabling trade-offs between minimizing the total traveled distance and the number of parallel transfer operations. Compared to the state-of-the-art scalable compiler for zoned architectures, our approach consistently finds fewer transfers. Depending on the optimization focus, our method produces shorter traveled distances or fewer parallel transfer operations. This work provides both theoretical guaranties and a practical tool for efficient, architecture-aware quantum circuit compilation. As a result, practitioners can generate hardware-aware mappings that reduce movement-induced errors and better exploit atom transfer parallelism, directly improving execution efficiency on NAQC devices.
Even as quantum computers continue to increase in number of qubits, high error rates limit the size of quantum circuits that can be executed. This results in low throughput and poor resource utilization on quantum computers. To address this, recent research has focused on extending circuit optimization and compilation techniques to support simultaneous execution of quantum circuits (i.e. quantum parallelism). While much work has been spent developing parallel mapping and gate scheduling techniques, there are few approaches to the problem of parallel job scheduling on quantum computers. There are several constraints that make quantum job scheduling different from classical scheduling. We propose a scheduling algorithm, QGroup, for parallelizing circuits of different lengths and shot counts while mitigating parallel slowdowns due to measurement synchronization. QGroup achieves a better parallelism-runtime tradeoff, with significant speedup and fidelity increase over existing methods. QGroup achieves improvement in both fidelity and runtime for noise-sensitive, diverse workloads.
Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n < m. In order to prevent cross-talk between two circuits, a buffer distance between their layouts is needed. Furthermore, not all the qubits and all the two-qubit interactions are at the same noise-level. Scheduling multiple circuits on the same hardware may create a possibility that some circuits are executed on a noisier layout than the others. In this paper, we consider an optimization problem which schedules as many circuits as possible for execution in parallel on the hardware, while maintaining a pre-defined layout quality for each. An integer linear programming formulation to ensure maximum fidelity while preserving the nearest neighbor arrangement among interacting qubits is presented. Our assertion is supported by comprehensive investigations involving various well-known quantum circuit benchmarks. As this scheduling problem is shown to be NP Hard, we also propose a greedy heuristic method which provides 2x and 3x better utilization for 27-qubit and 127-qubit hardware devices respectively in terms of qubits and time.