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Information systems engineering and management

Q-CODA: Co-designing Quantum Codes and Architectures for Hardware-Aware Quantum Error Correction

Pratik Thantharate, Anurag Thantharate

Published Jan 1, 2024• 4 citations
Publisher
DOI
10.1007/978-3-031-59318-5_11

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Asian Journal of Research in Computer Science•Dec 24, 2025•0 citations
Quantum computers are noisy; without quantum error correction (QEC), deep programs fail as qubits lose information due to decoherence. Among QEC approaches, bivariate bicycle (BB) codes offer low overhead and constant-depth syndrome extraction, while neutral-atom arrays provide scalable, reconfigurable qubit layouts. However, executing BB-code primitives on neutral-atom systems requires a hardware-aware mapping that respects movement, zoning, and interaction constraints. We present Park-n-Ride, a system for compiling and executing the BB code on neutral-atom processors. Park-n-Ride introduces a module layout and movement model aligned with neutral-atom constraints, exposes a compact BB-native logical interface for compilation, and integrates scheduling mechanisms that enable efficient execution on zoned architectures. By co-designing BB-code abstractions with hardware execution, Park-n-Ride provides a practical path from qLDPC primitives to resource-efficient, high-throughput execution on reconfigurable neutral-atom arrays.
Although quantum error correction is widely believed to be necessary for impactful applications of quantum computers, the design of quantum error correction codes is largely done by hand, without respect to problem or hardware constraints. In this work, we present a highly general and flexible framework for the computational design of both physics-inspired and hardware-aware quantum codes. To do so, we formulate code design as a Boolean satisfiability (SAT) problem and show how to incorporate all required error correction criteria. We prove that code design is NP-complete, ruling out any efficient algorithm for designing codes in general. Nonetheless, we show that state-of-the-art SAT solvers are able to effectively find solutions for many practical problems. Notably, we are able to design physics-inspired codes with up to 100 physical qubits in minutes, and we design new hardware-aware codes for biased noise which have a lower logical error rate than state-of-the-art surface codes.
Real-time decoding is a major bottleneck in scaling quantum error correction (QEC) from noisy intermediate-scale quantum (NISQ) devices to fault-tolerant quantum computing. We present an adaptive confidence-gated decoding framework for the rotated surface code that treats decoding as a two-stage inference problem. A lightweight feed-forward neural network performs fast-path decoding for the majority of syndrome measurements, while only low-confidence predictions are escalated to a minimum-weight perfect matching (MWPM) refinement stage. We benchmark the framework on rotated surface codes with distances d∈{3,5,7,9,11}d \in \{3,5,7,9,11\}d∈{3,5,7,9,11} under circuit-level depolarising noise using the Stim stabiliser simulator. The evaluation characterises logical accuracy, confidence-controlled accuracy-latency trade-offs, decoding throughput, per-shot latency, and decoding-graph resource scaling. Routing only 3.3%-6.2% of syndromes to the refinement stage improves logical accuracy from 99.21% for the neural-only baseline to 99.81% at a confidence threshold of 0.95 while incurring only a bounded increase in average decoding cost. Neural-decoder throughput saturates near 4.6×1054.6 \times 10^{5}4.6×105 samples s−1^{-1}−1 at batch size 512 on commodity CPU hardware, indicating that the neural fast path is not the dominant throughput bottleneck beyond code distance d=7d=7d=7. We release the complete benchmarking pipeline, trained models, raw benchmark data, and source code, and explicitly distinguish the experimentally validated contributions from the broader hardware-aware QEC co-design roadmap, including hardware-constrained code discovery, GPU-accelerated inference, and multi-noise optimisation, which remain directions for future work.
This review synthesizes current understanding of decoherence pathways across leading hardware platforms and explains why several experimentally observed noise features—drift, burst events, coherent components, correlated and non-Markovian structure, and leakage—can be disproportionately damaging for QEC. Decoherence remains the dominant impediment to scalable quantum computing because it is not a single error mechanism but a system-level phenomenon arising from materials defects, electromagnetic loss, control electronics, measurement backaction, and the broader environment in which a processor operates. Quantum error correction (QEC) is designed to algorithmically suppress physical noise, yet its practical success depends on how closely real devices satisfy the assumptions under which fault tolerance is proved: approximate locality, weak temporal correlations, sufficiently stochastic error statistics, low leakage, and reliable syndrome extraction. We then evaluate fundamental and engineering challenges that shape the viability of QEC at scale: syndrome measurement fidelity, correlated error suppression, decoding latency and classical co-processing, architectural constraints (connectivity, crosstalk, calibration overhead), and the resource cost of implementing a universal fault-tolerant gate set. Recent demonstrations of below-threshold behaviour and “break-even” regimes show that QEC is transitioning from theory to practice, but also clarify what remains unresolved: maintaining stable noise below fault-tolerance targets over long times, scaling to many logical qubits with low correlated-error rates, and integrating hardware-aware codes and decoders. We conclude with research priorities that treat decoherence and QEC as part of a co-designed stack spanning device physics, control, architecture, and algorithms.