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International Conference on Neural Networks, Information and Communication Engineering (NNICE)

Massive Parallel Simulation for Tensor Network Contraction Ordering Solving

Wei Xu, Weiqin Tong, Xiao-Yang Liu

Published Jan 19, 2024• 0 citations
Publisher

Abstract

Tensor network contraction is a powerful mathematical tool for dealing with complex systems and high-dimensional data, which is widely used in classical simulations of molecules and quantum circuits. To improve the performance of simulations, existing methods are implemented by searching the optimal contraction orderings for tensor networks. In particular, some reinforcement learning (RL) methods show a greater potential for solving. However, with the increasing scale of simulation, the number of tensors in the corresponding tensor network is huge, the existing RL methods suffer from sampling bottlenecks and slow solving speed, which make it difficult to efficiently solve for high-quality contraction orderings. In this paper, we design a massive parallel simulation environment for tensor network contraction ordering solving on a single GPU. We experimented with multiple numbers of parallel environments on the tensor-train network, and achieved the highest speedup when the number of environments was 26. We also have experimented on large-scale tensor-train networks and tree tensor networks, and compared to Kahypar and RL-Baseline, our method achieves average speedup of 8.96× and 7.48× on tensor-train networks, and 10.03× and 7.48× on tree tensor networks.

DOI
10.1109/nnice61279.2024.10498848

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Tensor network contraction is a powerful mathematical tool for dealing with complex systems and high-dimensional data, which is widely used in classical simulations of molecules and quantum circuits. To improve the performance of simulations, existing methods are implemented by searching the optimal contraction orderings for tensor networks. In particular, some reinforcement learning (RL) methods show a greater potential for solving. However, with the increasing scale of simulation, the number of tensors in the corresponding tensor network is huge, the existing RL methods suffer from sampling bottlenecks and slow solving speed, which make it difficult to efficiently solve for high-quality contraction orderings. In this paper, we design a massive parallel simulation environment for tensor network contraction ordering solving on a single GPU. We experimented with multiple numbers of parallel environments on the tensor-train network, and achieved the highest speedup when the number of environments was 26. We also have experimented on large-scale tensor-train networks and tree tensor networks, and compared to Kahypar and RL-Baseline, our method achieves average speedup of 8.96× and 7.48× on tensor-train networks, and 10.03× and 7.48× on tree tensor networks.
Tensor network contraction is a fundamental operation for dealing with high-dimensional data, which is now widely used in classical simulations of quantum circuits. To improve the performance of simulations, existing methods are implemented by optimizing contraction methods. However, with the increasing size of the tensor network, the contraction efficiency of these methods is difficult to satisfy the performance requirements and also suffers from the challenge of contracting tensor tasks that exceed GPU memory. In this paper, we propose a high-performance chunking method for tensor contraction. By chunking the given tensor, we obtain small tensors or vectors assign the corresponding threads, and contract them in parallel through the GPU. Solving high-order tensor contractions using distributed tensor contraction methods. Compared to the Einsum, our method achieves an average speedup of 22.28×. We also have experiments for large-scale tensor network contractions and our method achieves an average speedup of 13.56× compared to Tensordot.
Quantum Computing (QC) stands to revolutionize computing, but is currently still limited. To develop and test quantum algorithms today, quantum circuits are often simulated on classical computers. Simulating a complex quantum circuit requires computing the contraction of a large network of tensors. The order (path) of contraction can have a drastic effect on the computing cost, but finding an efficient order is a challenging combinatorial optimization problem. We propose a Reinforcement Learning (RL) approach combined with Graph Neural Networks (GNN) to address the contraction ordering problem. The problem is extremely challenging due to the huge search space, the heavy-tailed reward distribution, and the challenging credit assignment. We show how a carefully implemented RL-agent that uses a GNN as the basic policy construct can address these challenges and obtain significant improvements over state-of-the-art techniques in three varieties of circuits, including the largest scale networks used in contemporary QC.
One of the key problems in tensor network based quantum circuit simulation is the construction of a contraction tree which minimizes the cost of the simulation, where the cost can be expressed in the number of operations as a proxy for the simulation running time. This same problem arises in a variety of application areas, such as combinatorial scientific computing, marginalization in probabilistic graphical models, and solving constraint satisfaction problems. In this paper, we reduce the computationally hard portion of this problem to one of graph linear ordering, and demonstrate how existing approaches in this area can be utilized to achieve results up to several orders of magnitude better than existing state of the art methods for the same running time. To do so, we introduce a novel polynomial time algorithm for constructing an optimal contraction tree from a given order. Furthermore, we introduce a fast and high quality linear ordering solver, and demonstrate its applicability as a heuristic for providing orderings for contraction trees. Finally, we compare our solver with competing methods for constructing contraction trees in quantum circuit simulation on a collection of randomly generated Quantum Approximate Optimization Algorithm Max Cut circuits and show that our method achieves superior results on a majority of tested quantum circuits. Reproducibility: Our source code and data are available at https://github.com/cameton/HPEC2022_ContractionTrees.
Exact tensor network contraction underpins quantum circuit simulation, quantum error correction, combinatorial optimization, and many-body dynamics. The dominant parallelization strategy, slicing, scales exponentially and incurs redundant computation. We present a multi-GPU framework that instead distributes intermediate tensors across devices with explicit communication, converting a fixed contraction path into a communication-efficient schedule via GEMM-oriented mode reordering and communication-aware mode distribution planning. Within a single DGX H100 node (8 GPUs, NVLink), distribution delivers 777--173×173\times173× extra speedup beyond embarrassingly parallel slicing, capturing nearly all of the available compute reduction (87--101%) because NVLink's high bandwidth keeps communication small relative to compute. Scaling the same four workloads to 1024 H100 GPUs over InfiniBand, the extra speedup beyond slicing ranges from 42×42\times42× to 67,869×67{,}869\times67,869×, demonstrating that communication-aware distributed contraction far surpasses slicing-based scaling limits for frontier tensor networks.
Large-scale tensor network simulations are crucial for developing robust complexity-theoretic bounds on classical quantum simulation, enabling circuit cutting approaches, and optimizing circuit compilation, all of which aid efficient quantum computation on limited quantum resources. Modern exascale high-performance computing platforms offer significant potential for advancing tensor network quantum circuit simulation capabilities. We implement TN-Sim, a tensor network simulator backend within the NWQ-Sim software package that utilizes the Tensor Algebra for Many-body Methods (TAMM) framework to support both distributed HPC-scale computations and local simulations with ITensor. To optimize the scale up in computation across multiple nodes we implement a task based parallelization scheme to demonstrate parallelized gate contraction for wide quantum circuits with many gates per layer. Through the integration of the TAMM framework with Matrix Product State (MPS) tensor network approaches, we deliver a simulation environment that can scale from local systems to HPC clusters. We demonstrate an MPS tensor network simulator running on the state-of-the-art Perlmutter (NVIDIA) supercomputer and discuss the potential portability of this software to HPC clusters such as Frontier (AMD) and Aurora (Intel). We also discuss future improvements including support for different tensor network topologies and enhanced computational efficiency.
Tensor networks represent the state-of-the-art in computational methods across many disciplines, including the classical simulation of quantum many-body systems and quantum circuits. Several applications of current interest give rise to tensor networks with irregular geometries. Finding the best possible contraction path for such networks is a central problem, with an exponential effect on computation time and memory footprint. In this work, we implement new randomized protocols that find very high quality contraction paths for arbitrary and large tensor networks. We test our methods on a variety of benchmarks, including the random quantum circuit instances recently implemented on Google quantum chips. We find that the paths obtained can be very close to optimal, and often many orders or magnitude better than the most established approaches. As different underlying geometries suit different methods, we also introduce a hyper-optimization approach, where both the method applied and its algorithmic parameters are tuned during the path finding. The increase in quality of contraction schemes found has significant practical implications for the simulation of quantum many-body systems and particularly for the benchmarking of new quantum chips. Concretely, we estimate a speed-up of over 10,000 × compared to the original expectation for the classical simulation of the Sycamore `supremacy' circuits.