An alternative quantum order-finding algorithm is proposed, suitable for implementing on Noisy Intermediate-Scale Quantum (NISQ) devices. In particular, the proposed algorithm bypasses the modular exponentiation and the quantum Fourier transform required in the traditional approach to order-finding. Instead, our algorithm involves an approximate implementation of the square root of a permutation unitary, which requires demonstrably fewer resources in comparison to the standard approach as well as other recently proposed NISQ-era algorithms for order-finding. We obtain heuristic bounds on the circuit complexity of our proposed algorithm and numerically estimate the error incurred due to the approximation involved. Finally, we implement our algorithm on IBM quantum machines with and without error mitigation and benchmark its performance.
An alternative quantum order-finding algorithm is proposed, suitable for implementing on Noisy Intermediate-Scale Quantum (NISQ) devices. In particular, the proposed algorithm bypasses the modular exponentiation and the quantum Fourier transform required in the traditional approach to order-finding. Instead, our algorithm involves an approximate implementation of the square root of a permutation unitary, which requires demonstrably fewer resources in comparison to the standard approach as well as other recently proposed NISQ-era algorithms for order-finding. We obtain heuristic bounds on the circuit complexity of our proposed algorithm and numerically estimate the error incurred due to the approximation involved. Finally, we implement our algorithm on IBM quantum machines with and without error mitigation and benchmark its performance.
Noisy intermediate-scale quantum (NISQ) computers face significant reliability challenges because they are vulnerable to quantum noise, which severely limits their fidelity in quantum applications. In particular, deep circuits with a large number of quantum gates are susceptible to errors as they are more likely to lose their states in a deep circuit. In this paper, we propose a quantum circuit for square root operation that generates correct results on NISQ devices. The square root operation is used in many applications such as complex number computations, computer graphics, etc. While there have been limited studies on quantum square root circuits, none of them can be implemented on NISQ devices. In this work, we simplify the structure of an exact quantum square root circuit and reduce the number of quantum gates. The proposed design reduces the complexity of the square root circuit while maintaining the same level of precision in outputs. In addition, we exploit approximate computing to simplify the circuit further and run it on a real quantum computer. Approximate computing is used in classical computers to enhance the power and/or performance in exchange for accuracy. We exploit approximate computing for a different purpose, which is reducing the depth as well as the number of quantum gates in the square root circuit. To validate the effectiveness of our approach, we conduct experiments on an IBM quantum computer, where our circuit produces meaningful results. Furthermore, we present examples of error-resilient applications to demonstrate the validity of our approximate circuit.
Quantum computing has the potential to solve complex problems that are outside the scope of classical systems, making it a standard shifter. Current devices, which are considered as Noisy Intermediate-Scale Quantum (NISQ) systems, are insufficient in their practical utility due to hardware limitations, error rates, and qubit counts. The dynamic growths wanted to exceed the NISQ era and grow scalable quantum algorithms and architectures that can achieve useful quantum benefit in real-world applications are reviewed in this research. This research gives a comprehensive examination of the complications in scaling quantum systems, adjacent resource efficacy, qubit connectivity, and error correction. In addition to connecting architectural innovations like modular quantum computing, error-resilient circuit design, and distributed quantum systems, the paper provides new hybrid quantum-classical algorithms planned to exploit performance in noisy environments. Results from benchmarking in arenas like machine learning, optimization, and quantum chemistry show how these methods can provide short-term quantum benefit. Lastly, this paper proposes a research roadmap for quantum computing that highlights the requirement of co-designing algorithms, software, and hardware. The goal of this effort is to straighten the progress of quantum systems that can resolve problems in the real world at scale by addressing the inadequacies of NISQ devices and emphasizing scalable solutions.
Quantum phase estimation (QPE) is one of the core algorithms for quantum computing. It has been extensively studied and applied in a variety of quantum applications such as the Shor's factoring algorithm, quantum sampling algorithms and the calculation of the eigenvalues of unitary matrices. The QPE algorithm has been combined with Kitaev's algorithm and the inverse quantum Fourier transform (IQFT) which are utilized as a fundamental component of such quantum algorithms. In this paper, we explore the computational challenges of implementing QPE algorithms on noisy intermediate-scale quantum (NISQ) machines using the IBM Q Experience (e.g., the IBMQX4, 5-qubit quantum computing hardware platform). Our experimental results indicate that the accuracy of finding the phase using these QPE algorithms is severely constrained by the NISQ computer's physical characteristics such as coherence time and error rates. To mitigate these physical limitations, we propose implementing a modified solution by reducing the number of controlled rotation gates and phase shift operations, thereby increasing the accuracy of the finding phase in near-term quantum computers.
In the near future of the noisy intermediate-scale quantum (NISQ) era, almost all quantum computing devices will be restricted to a specific fixed qubits connectivity architecture. Thus, the synthesis of quantum circuits with limited connectivity is urgent. We design quantum circuit synthesis algorithms for basic and essential synthesis problems, such as quantum state preparation, general unitary synthesis, and quantum isometries. For any architecture, the controlled not (cnot) count is at most 5/3 times the state-of-the-art result on complete-graph architecture. For some specific architectures, such as square-grid ones, the ratio is reduced to 1.126. The numerical simulation result is confirmatory of theoretical conclusions. Our algorithms significantly reduce by more than 50 additional cnot count compared to mapping algorithms. These algorithms help to implement the larger-scale algorithm in the physics device. Our results illustrate that well-designed synthesis algorithms can mitigate the problem of limited qubit connectivity in the NISQ era and may suggest the design of large-scale quantum devices.
This paper addresses the practical aspects of quantum algorithms used in numerical integration, specifically their implementation on Noisy Intermediate-Scale Quantum (NISQ) devices. Quantum algorithms for numerical integration utilize Quantum Amplitude Estimation (QAE) (Brassard et al., 2002) in conjunction with Grover’s algorithm. However, QAE is daunting to implement on NISQ devices since it typically relies on Quantum Phase Estimation (QPE), which requires many ancilla qubits and controlled operations. To mitigate these challenges, a recently published QAE algorithm (Suzuki et al., 2020), which does not rely on QPE, requires a much smaller number of controlled operations and does not require ancilla qubits. We implement this new algorithm for numerical integration on IBM quantum devices using Qiskit and optimize the circuit on each target device. We discuss the application of this algorithm on two qubits and its scalability to more than two qubits on NISQ devices.
Increasing the utility of currently available Noisy Intermediate-Scale Quantum (NISQ) devices requires developing efficient methods to mitigate hardware errors. In this work we propose a novel Cyclic Layout Permutations-based Zero-Noise Extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent non-uniformity of gate errors in NISQ hardware to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. In contrast to the previous layout permutation based approaches, for an n-qubit circuit CLP-ZNE requires execution of only O(n) and at most O(n2) different circuit layouts for circuits of one-dimensional and arbitrary connectivity, respectively. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical error in expectation values of n=12 qubit circuits by an order of magnitude, outperforming standard unitary folding ZNE. By demonstrating the ability to mitigate noise of real hardware specifications, including both depolarizing and T1/T2 relaxation processes, these results give evidence for the applicability of CLP-ZNE to present-day NISQ processors.