Large-scale CMOS annealing processors are being developed to solve combinatorial optimization problems in society. Although it has been difficult to implement fully coupled annealing processors on multiple chips due to the complexity of the coupling, it is possible to scale by dividing a part of the calculation. In this work, we aim to realize a 4096 spin scalable fully coupled annealing processing system with 38 chips. For this purpose, we fabricated and evaluated the A-chip LSI that serves as the core in this system. We also reduced the number of required A-chips by 43.75% by reducing the interactions that occupy most of the area. In addition, we introduced spin threads to improve solution accuracy.
Large-scale CMOS annealing processors are being developed to solve combinatorial optimization problems in society. Although it has been difficult to implement fully coupled annealing processors on multiple chips due to the complexity of the coupling, it is possible to scale by dividing a part of the calculation. In this work, we aim to realize a 4096 spin scalable fully coupled annealing processing system with 38 chips. For this purpose, we fabricated and evaluated the A-chip LSI that serves as the core in this system. We also reduced the number of required A-chips by 43.75% by reducing the interactions that occupy most of the area. In addition, we introduced spin threads to improve solution accuracy.
There has been progress in annealing processors for solving combinatorial optimization problems. There are two types of annealing processors: the "sparsely coupled" type, which implements only some spin-to-spin couplings, and the "fully coupled" type, which implements all spin-to-spin couplings. The latter has the advantage of having a large number of problems to be solved per spin, but had been said to have the disadvantage of poor scalability due to the complicated coupling. To overcome this, we first created a scalable Fully coupled annealing processing system (SFCAPS) by using multi-chip operation and implemented it on an FPGA board. This is to reduce the amount of coupling per chip by performing the multi-chip operation, and to improve the scalability by facilitating the connection between the chips. However, in the architecture, multi-chip operation could not be fully used and most of the chips on the board were idle for a large amount of time. Therefore, for this study, we implemented a parallel annealing method called multi-spin threading on this architecture to reduce the number of idle chips and demonstrated that the architecture can operate more efficiently. As a result, the architecture became more efficient, which raised the parallelism of the architecture. This has resulted in an average 5% improvement in the accuracy of the annealing processor's solution, demonstrating that it is easier to achieve a high accuracy solution.
Annealing processors (APs) specialized for solving combinatorial optimization problems (COPs) have been gaining attention. Among them, APs that use a fully-coupled Ising model are in demand because of their versatility. However, due to the complexity of the spin couplings, challenges remain in achieving systems that balance both capacity (number of spins) and precision (interaction bit width). Previous studies have implemented annealing systems that only increase the number of spins using a scalable structure by distributing the calculation across multiple chips. This study proposes a dual scalable annealing processing system (DSAPS) that can simultaneously scale both capacity and precision using the same scalable structure. This demonstrates a new direction that combines both the number of spins and interaction bit width. A board implementation utilized spin threads to create two types of DSAPS: DSAPS #1, with 2048 spins, 10-bit interactions and four threads, and DSAPS #2, with 1024 spins, 37-bit interactions and two threads. Scaled MAX-CUT problems were used for operational validation, achieving an accuracy of over 99% compared with theoretical values. In another validation using the 0-1 knapsack problem, DSAPS #1 achieved an average deviation of over 99% relative to the knapsack capacity, whereas DSAPS #2 reduced the average deviation to 0.73%. This result is close to the average deviation of 0.40% obtained with an annealing emulation on a CPU (64-bit), demonstrating the significance of implementing DSAPSs suited to the characteristics of COPs.
This research is concerned with an annealing processor for efficiently solving a combinatorial optimization problem.\nIn order to realize a smart society, optimization of people and thingssuch as transportation networks, power networks, human resource allocationand routes is indispensable. Many of these problems are called combinatorial optimization problems and are known as very important problems in modern society. However, it is known that the combinatorial optimization problem is NP-hard and it is difficult to efficiently solve it with a conventional Neumann computer.\nIn recent years, the miniaturization of the process of manufacturing computer chips is approaching the physical limit. Therefore, especially in the solution by the full search, the improvement in speed due to the calculation speed of the computer cannot be expected. From such a background, dedicated hardware capable of solving a combination optimization problem at high speed and with low power consumption has been attracting attention.\nThe annealing processor is a general-purpose combination optimization solver that utilizes the property that the ground state of the optimization problem expressed by using the Ising model and the optimal solution of the combination optimization problem match. The Ising model is a ferromagnetic model in statistical physics expressed by spins having an upward and downward state, spin-spin interactions occurring between the spins, and an external magnetic field acting on each spin. The Ising model can express a combinatorial optimization problem by expressing a control target and a cost using these parameters. The annealing processor updates the spin state while slowly lowering the temperature parameters based on simulated annealing,which is an optimization method learned from natural phenomena generally called annealing. Eventually, the spin will reach the ground state with a high probability and obtain the optimal solution.\nAnnealing processors are classified into two types, the nearest neighbor type and the fully connected type, depending on the shape of the Ising model simulated on the hardware. In the nearest neighbor type, the coupling between spins is limited to only between adjacent spins, and in the full coupling type, coupling exists between arbitrary spins. The nearest neighbor type realizes high parallel processing by reducing the data spin required by simulated annealing by reducing the proximity spin. In addition, since data transfer is limited to adjacent spins, the scalability is high. However, since the spin-to-spin interaction is sparse, there is a problem that the class of combinatorial optimization problems that can be dealt with is limited, or that the problem requires deformation processing to match the Ising model of hardware. The fully connected type can solve any class of problems as long as the number of spins permits, however it requires connections between arbitrary spins.Therefore, scalability is low. Because there there is a dependency on all spins,the number of spins that can be updated at one time is always limited to only one regardless of the total number of spins. Therefore, it takes time to converge to the ground state.\nIn this research, we propose a method of increasing the number of spins for this annealing processor by using (1) a spatially-expanded time-division processing mechanism architecture based on a loosely-coupled type, (2) An algorithm for applying a fully coupled Ising network to a more complex Ising network using the nearest neighbor Ising network and an annealing method that can be updated in parallel, (3)We conducted a study on the architecture of a fully coupled annealing processor for parallel updating annealing.\nAs described above, the research described in this paper contributes to the improvement of the efficiency of the annealing processor for solving the large-scale combinatorial optimization problem from both the fundamental algorithm and the hardware architecture. I hope that this research will solve the combinatorial optimization problem that is expected to increase in demand in the future and contribute to the development of human society.
The development of annealing processors has progressed as a solution to large-scale combinatorial optimization problems. Inside a fully-coupled annealing machine that can handle a wide range of combinatorial optimization problems, there are elements called interactions that indicate the force between spins, the number of which is the square of the number of spins. However, the area of the circuit is greatly restricted. Therefore, we focus on the symmetry of interactions and propose a method for reducing the number of interactions by giving regularity to the two-dimensional arrangement of interactions. The interaction halving method has a high affinity with the previously published scalable fully-coupled annealing machine, and the interaction proposed this time for the 384-spin full-coupled annealing machine using 16 Field Programmable Gate Array chips shown in previous research. By applying the reduction method, we succeeded in implementing two independent 384-spin fully coupled annealing machines with 16 chips.
Annealing processors (AP) specializing in solving combinatorial optimization problems have attracted attention. From the perspective of versatility, there has been a demand for fully-coupled Ising model-based AP, but challenges remain in achieving a system that combines both capacity (number of spins) and precision (interaction bit width) due to the complexity of the coupling. This study proposed a Dual Scalable Annealing Processing System (DSAPS) that can simultaneously scale the number of spins and interaction bit width using the same scalable structure. This introduces a new direction in scalability that combines both capacity and precision, compared to previous approaches that focused solely on capacity. A DSAPS with 2,048-spin and 10-bit interaction was implemented on an actual board. Four scaled MAX-CUT problems were used for operational validation, achieving accuracy of over 97 % compared with theoretical values. Compared to CPU simulation for a weighted MAX-CUT problem, the average cut value error was limited to 0.912 %. Furthermore, the average cut value of DSAPS was 2.93 % closer to that of CPU simulation than the 4 bit interaction board. These results confirm the utility of the proposed system and its new scaling direction.
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The main feature of this processor is its inter-chip connection interface for making a larger chip. A credit card sized compute node integrating two CMOS-APs was also developed as an interface with existing computer systems. The compute node can handle up to 61,952 spins at a time. A performance evaluation using the node improved the CPU speed by 55 times in solving a minimum vertex cover problem, one of the NP-hard combinatorial optimization problems. Finally, we describe a cloud interface for the compute node to make the CMOS-APs more useful and to promote application development for it.