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Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations

David Clarino, Naoya Asada, Shigeru Yamashita

Published Oct 28, 2023• 1 citation
Publisher

Abstract

LUT-based synthesis methods have recently been proposed as a way to synthesize quantum Boolean circuits in a qubit constrained environment. Other results have also shown that allowing a relative phase when implementing quantum Boolean circuits yields an advantage in T-count without additional ancilla qubits, which is advantageous in the fault-tolerant quantum computing paradigm. We propose a method that utilizes both LUT-based synthesis and relative phase quantum Boolean circuits which minimize the T-count while minimizing the ancilla required to implement them. We leverage recent results regarding relative phase versions of Boolean functions and Shannon's decomposition to propose a novel method to synthesize arbitrary Boolean functions up to a relative phase. We then utilize this method to synthesize Boolean logic inside each LUT as a relative phase quantum Boolean circuit and show that the resulting quantum circuit has a clear advantage in T-count over more naive methods.

DOI
10.1109/iccad57390.2023.10323730

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LUT-based synthesis methods have recently been proposed as a way to synthesize quantum Boolean circuits in a qubit constrained environment. Other results have also shown that allowing a relative phase when implementing quantum Boolean circuits yields an advantage in T-count without additional ancilla qubits, which is advantageous in the fault-tolerant quantum computing paradigm. We propose a method that utilizes both LUT-based synthesis and relative phase quantum Boolean circuits which minimize the T-count while minimizing the ancilla required to implement them. We leverage recent results regarding relative phase versions of Boolean functions and Shannon's decomposition to propose a novel method to synthesize arbitrary Boolean functions up to a relative phase. We then utilize this method to synthesize Boolean logic inside each LUT as a relative phase quantum Boolean circuit and show that the resulting quantum circuit has a clear advantage in T-count over more naive methods.
Lookup Table (LUT) based synthesis methods have recently been proposed as a way to synthesize quantum Boolean circuits in a qubit-constrained environment. Other recent research papers have demonstrated the possibility of using relative phase quantum circuits when compute/uncompute logic is used in tandem, reducing T-count in quantum Boolean circuits in the fault-tolerant quantum computing paradigm. Because LUT-based synthesis methods use compute/uncompute pairs on ancilla qubits, this suggests that implementing the arbitrary Boolean logic that make up the individual Boolean logic network nodes in a relative phase manner could reduce the T-count. To generate such arbitrary Boolean functions, we utilize Shannon’s decomposition, Davio expansions, as well as alternating balanced and unbalanced relative phase circuits. Experimental results demonstrate that our method can reduce the T-count to an average of 24% of the existing method.
In fault-tolerant quantum circuit synthesis, T gates supplied via magic states dominate space-time cost, while Clifford gates incur negligible overhead. Conventional flows minimize AND count in an {XOR, AND, NOT} basis as a proxy for T, which neglects phase cancellation and can be far from T-optimal. We instead formulate an exact T synthesis problem and canonicalize Boolean functions under Clifford equivalence. By precomputing T-optimal implementations up to seven variables and developing a customized mapper, we reduce the T count by up to 14.3% on EPFL benchmarks and improve the T counts of several cryptographic modules by up to 40%.
Decoherence jeopardizes the entanglement of fragile quantum states, and is among the foremost challenges towards engineering scalable quantum computers. Realizing quantum circuit implementation with small qubit count and shallow circuit depth is necessary due to the linear scaling of decoherence rate with qubit count and circuit depth. Conversely, reasonable correction of small unitary errors can be achieved by using surface codes along with a transversal gate set to protect quantum information from decoherence. In this paper, we analyze and report the upper bound of non-Clifford phase-depth for different mapping schemes and synthesis approaches. We introduce a synthesis methodology based on lookup-table (LUT) networks, wherein the Boolean logic translates into fault-tolerant quantum logic using Clifford+ Z N group with zero ancillary cost. We also present fault-tolerant synthesis techniques for k -LUT network using additional ancillary lines with exponential phase-count and unit phase-depth.
The quantum circuit is the prime factor to realize quantum computation. This paper proposes a novel quantum-inspired evolutionary computation method to synthesize quantum circuits effectively and efficiently. Recently, the Clifford+T gate library has become popular, as the T gate has a better fault-tolerant and error correction efficacy, which is essential to near-term quantum computation. The proposed quantum-inspired evolutionary computation is more flexible in constructing diverse solutions than the classical synthesis method. The entangled local search mechanism further enhances the ability to discover the optimal solutions on an efficient frontier. The encoding can be slightly changed to achieve various gate libraries circuit synthesis in the quantum or reversible Boolean circuits. The experiments demonstrate that our proposed method can be more effective in composing a compact quantum circuit than the state-of-the-art method. Meanwhile, the T-depth can attain an optimal value without ancilla bits. Furthermore, we provide an illustration to construct the function equivalent quantum circuit with the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV). We also conduct exhaustion to prove that our synthesized circuit is an optimal solution, requiring far fewer resources in time and evaluation than exhaustion.
We propose a method for exact circuit synthesis using a discrete gate set, as required for fault-tolerant quantum computing. Our approach translates the problem of synthesizing a gate specified by its unitary matrix into a boolean satisfiability (SAT) instance. It leverages the algebraic properties of the coefficients of the matrices that constitute the gate set, enabling the transformation of the constraint of equality between complex matrices into a boolean expression to satisfy. For a specified number of gates, the SAT solver finds a circuit implementing the target or proves that none exist. Optimality of the number of gates is proven by iterating on the number of gates. We also propose some extensions of the method, for example, handling ancillary qubits, post-selection, or classical feedback. The time-to-solution scales double-exponentially with the number of qubits, making it impractical for large circuits. However, since many quantum algorithms rely on small, frequently used subcircuits, and because of the intrinsic value of having a provably optimal circuit synthesis, we believe that our tool are valuable for quantum circuit design.
Quantum circuit synthesis, the process of mapping logical operations onto a quantum hardware architecture, presents a significant bottleneck in the development of practical quantum computers. Traditional methods often suffer from exponential computational complexity, rendering them unsuitable for circuits of even moderate size. This work introduces a novel approach to quantum circuit synthesis leveraging topological optimization, a technique rooted in condensed matter physics. We represent quantum circuits as topological phases on a graph, where gate operations are encoded as transitions between these phases. An iterative optimization process then refines the graph structure, minimizing circuit complexity (represented as energy) while maintaining the desired quantum operations. The core of our method lies in the application of gradient-based optimization algorithms to this topological graph, driving the system towards a low-energy state representing an optimal quantum circuit. Preliminary results demonstrate the potential of this approach to significantly reduce gate count and improve fidelity compared to conventional synthesis methods. The proposed framework offers a scalable solution to the challenges inherent in quantum circuit design, paving the way for more efficient and reliable quantum computation.