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Optics Express

High-speed information reconciliation with syndrome-based early termination for continuous-variable quantum key distribution

Kun Zhang, Jia Hou, Xueqin Jiang, Enjian Bai, Peng Huang, Guihua Zeng

Published Sep 14, 2023• 10 citations
Publisher

Abstract

Information reconciliation (IR) is an indispensable component in the post-processing stage of continuous-variable quantum key distribution (CV-QKD), which adopts error-correcting codes to address the asymmetry of secret keys. Currently, low-density parity-check (LDPC) decoding in IR is a post-processing bottleneck in high-speed CV-QKD systems since the upper bound on secret key rate is higher than the information throughput delivered by decoder. In this paper, we study the relationship between the syndrome variation pattern (SVP) in iterative decoding and reconciliation frame error rate. An early termination scheme based on SVP is proposed and applied to multidimensional reconciliation, which can increase information throughput by adaptively adjusting the iteration number of iterative decoding to real-time decoding status. Furthermore, we show that only the resulting syndrome of the highest-rate code part in Raptor-like LDPC codes needs to be calculated to verify whether the reconciliation is successful by studying the convergency of resulting syndrome, which can save a large fraction of computational resources for syndrome calculation. Simulation results show that information throughput of the proposed scheme can be improved by 617.1% compared to the existing scheme when the IR efficiency reaches 97.09%. The proposed scheme points out a new direction for breaking the post-processing bottleneck in high-speed CV-QKD systems.

DOI
10.1364/oe.494078

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Information reconciliation (IR) is an indispensable component in the post-processing stage of continuous-variable quantum key distribution (CV-QKD), which adopts error-correcting codes to address the asymmetry of secret keys. Currently, low-density parity-check (LDPC) decoding in IR is a post-processing bottleneck in high-speed CV-QKD systems since the upper bound on secret key rate is higher than the information throughput delivered by decoder. In this paper, we study the relationship between the syndrome variation pattern (SVP) in iterative decoding and reconciliation frame error rate. An early termination scheme based on SVP is proposed and applied to multidimensional reconciliation, which can increase information throughput by adaptively adjusting the iteration number of iterative decoding to real-time decoding status. Furthermore, we show that only the resulting syndrome of the highest-rate code part in Raptor-like LDPC codes needs to be calculated to verify whether the reconciliation is successful by studying the convergency of resulting syndrome, which can save a large fraction of computational resources for syndrome calculation. Simulation results show that information throughput of the proposed scheme can be improved by 617.1% compared to the existing scheme when the IR efficiency reaches 97.09%. The proposed scheme points out a new direction for breaking the post-processing bottleneck in high-speed CV-QKD systems.
The information reconciliation (IR) stage is a critical component of post-processing in continuous-variable quantum key distribution (CV-QKD), which is essential to ensure high secret key rates and long transmission distances. Currently, improving reconciliation efficiency is a key research focus in the CV-QKD field. Additionally, the low-density parity-check (LDPC) decoding speed in IR is a post-processing bottleneck in high-speed CV-QKD. In this paper, we propose a construction scheme for spatially coupled (SC) LDPC codes in CV-QKD systems and maintain a constant code rate when extending the code length as required. Furthermore, we investigate the relationship between the syndrome variation pattern (SVP) and the frame error rate. Adaptively adjusting the number of decoding iterations according to the distinct convergence behaviors of the SVP, the convergence-based early termination (C-ET) scheme is proposed, which can reduce invalid iterations. The simulation results show that the proposed construction scheme for SC-LDPC codes can improve the reconciliation efficiency to 97% and achieve a flexible code length. The C-ET scheme achieves a 292% improvement in information throughput compared to the original ET scheme when the reconciliation efficiency reaches 97%. Moreover, the C-ET scheme also achieves a reduction in decoding latency compared to the existing syndrome-based early termination scheme. These advances provide a substantial step toward improving reconciliation efficiency and breaking the post-processing bottleneck in CV-QKD systems.
In continuous-variable (CV) quantum key distribution (QKD), the reconciliation efficiency and frame error rate of the information reconciliation have a significant impact on the secret key rate. For a fixed-rate multiedge-type low-density parity-check (LDPC) code, the reconciliation efficiency and frame error rate will inevitably vary due to the fluctuations of the signal-to-noise ratio (SNR) of the CV QKD system, which degrades the performance of the system. We propose a high-efficiency rate-adaptive information reconciliation scheme by combining raptorlike (RL) LDPC codes with the addition of trusted noises. We establish the model of adding trusted noises and combine it with the RL LDPC codes to optimize the secret key rate under the time-varying channel. The simulation results show that our scheme can maintain a high reconciliation efficiency of more than 94.4% and a low frame error rate within 15% fluctuation range of the SNR. Furthermore, we implement the hardware acceleration of the proposed rate-adaptive scheme on a graphics processing unit and achieve a decoding throughput of 65.5 Mbits/s by optimizing the storage of the parity-check matrix. Our results are useful for the practical CV QKD under the realistic time-varying channel.
Reconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
The throughput of error correction is the main bottleneck of continuous variable quantum key distribution (CV-QKD) postprocessing. Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA with limited precision can improve the decoding throughput significantly. However, the limited precision on FPGA results in the existence of residual error-bits after decoding, which lowers the secret key rate and restricts the application of high-rate real-time CVQKD system. In this paper, an efficient decoding scheme is proposed to erase the residual error-bits and decrease the frame errors rate (FER), where the decoding process into two stages and some values of initial Log Likelihood Ratio (LLR) are adjusted according to the proposed principles before starting the second-stage decoding. For the rates 0.2 and 0.1 LDPC codes, numerical results demonstrate that the proposed decoding scheme decreases the FER obviously and the throughputs of 152.47Mbps and 88.32Mbps are achieved, which can be applied to support high-speed CV-QKD system under transmission distance of 25km and 50km respectively.
Reconciliation is a significant procedure in a continuous-variable quantum key distribution (CV-QKD) system. It is employed to extract secure secret key from the resulted string through quantum channel between two users. However, the efficiency and the speed of previous reconciliation algorithms are low. These problems limit the secure communication distance and the secure key rate of CV-QKD systems. In this paper, we proposed a high-speed reconciliation algorithm through employing a well-structured decoding scheme based on low density parity-check (LDPC) code. The complexity of the proposed algorithm is reduced obviously. By using a graphics processing unit (GPU) device, our method may reach a reconciliation speed of 25 Mb/s for a CV-QKD system, which is currently the highest level and paves the way to high-speed CV-QKD.