The challenge of mapping logical qubits to physical qubits in quantum systems has been addressed in prior proposals that optimize the Probability of Successful Trial (PST) by considering the coherence and gate error rates. However, these proposals do not account for crosstalk errors, which occur when active qubits interact during execution. The reason for this is that crosstalk only appears after the initial mapping, while previous strategies allocate qubits based on program and quantum system characteristics using one-step mapping methods. Scheduling-based solutions have been created to address this problem by inserting barriers between gates to reduce crosstalk, but at the expense of increased execution time and coherence error rates, ultimately decreasing overall accuracy. This paper presents and evaluates TRIM, a novel strategy that characterizes crosstalk and eliminates it in an iterative fashion using a multi-step greedy search method, which can be applied to any qubit mapping to reduce crosstalk while keeping execution time and coherence errors in check. Evaluations of TRIM using multiple workloads show PST improvements of 7.3% for single-programmed execution and 7.7% for multiprogramming scenarios, while reducing or keeping the number of gates, compared to a state-of-the-art mapping scheme. Additionally, TRIM achieves 5.4% and 3.3% PST improvements for single-programmed and multiprogrammed executions, respectively, compared to a state-of-the-art scheduling strategy.
The challenge of mapping logical qubits to physical qubits in quantum systems has been addressed in prior proposals that optimize the Probability of Successful Trial (PST) by considering the coherence and gate error rates. However, these proposals do not account for crosstalk errors, which occur when active qubits interact during execution. The reason for this is that crosstalk only appears after the initial mapping, while previous strategies allocate qubits based on program and quantum system characteristics using one-step mapping methods. Scheduling-based solutions have been created to address this problem by inserting barriers between gates to reduce crosstalk, but at the expense of increased execution time and coherence error rates, ultimately decreasing overall accuracy. This paper presents and evaluates TRIM, a novel strategy that characterizes crosstalk and eliminates it in an iterative fashion using a multi-step greedy search method, which can be applied to any qubit mapping to reduce crosstalk while keeping execution time and coherence errors in check. Evaluations of TRIM using multiple workloads show PST improvements of 7.3% for single-programmed execution and 7.7% for multiprogramming scenarios, while reducing or keeping the number of gates, compared to a state-of-the-art mapping scheme. Additionally, TRIM achieves 5.4% and 3.3% PST improvements for single-programmed and multiprogrammed executions, respectively, compared to a state-of-the-art scheduling strategy.
Crosstalk poses a significant challenge in quantum computing, particularly when quantum gates are executed in parallel, as qubit frequency resonance can lead to residual coupling and reduced gate fidelity. Current solutions struggle to mitigate both crosstalk and decoherence during parallel two-qubit gate operations on frequency-tunable quantum chips. To address this, we propose a crosstalk-aware mapping and gate scheduling (CAMEL) approach, designed to mitigate crosstalk and suppress decoherence by leveraging the tunable coupler’s physical properties and incorporating a pulse compensation technique. CAMEL operates within a two-step compilation framework: first, a qubit mapping strategy that considers both crosstalk and decoherence; and second, a gate timing scheduling method that prioritizes the execution of the largest possible set of crosstalk-free parallel gates, reducing overall circuit execution time. Evaluation results demonstrate CAMEL’s superior ability to mitigate crosstalk compared to crosstalk-agnostic methods, while successfully suppressing decoherence where other approaches fail. Additionally, CAMEL performs better than dynamic-frequency-aware techniques, particularly in low-complexity hardware environments.
Crosstalk is a major source of noise in Noisy Intermediate-Scale Quantum (NISQ) systems and is a fundamental challenge for hardware design. When multiple instructions are executed in parallel, crosstalk between the instructions can corrupt the quantum state and lead to incorrect program execution. Our goal is to mitigate the application impact of crosstalk noise through software techniques. This requires (i) accurate characterization of hardware crosstalk, and (ii) intelligent instruction scheduling to serialize the affected operations. Since crosstalk characterization is computationally expensive, we develop optimizations which reduce the characterization overhead. On 3 20-qubit IBMQ systems, we demonstrate two orders of magnitude reduction in characterization time (compute time on the QC device) compared to all-pairs crosstalk measurements. Informed by these characterization, we develop a scheduler that judiciously serializes high crosstalk instructions balancing the need to mitigate crosstalk and exponential decoherence errors from serialization. On real-system runs on 3 IBMQ systems, our scheduler improves the error rate of application circuits by up to 5.6x, compared to the IBM instruction scheduler and offers near-optimal crosstalk mitigation in practice.
ZZ crosstalk and decoherence hinder superconducting quantum computing. Mitigation strategies often require sequential gate execution, which restricts parallelism. We reformulate ZZ crosstalk mitigation as a parallel task scheduling problem by integrating quantum cycles and qubit interference. We then propose CYCO, a CYcle-aware ZZ Crosstalk Optimization algorithm, which uses a timing-based greedy strategy to schedule gates through cycles within quantum circuits. A novel data structure called Time and Distance Dependency Graph (TDDG) is designed to model gate dependencies and physical qubit distances. Based on TDDG, barrier punching is introduced to eliminate redundant synchronization barriers by merging independent gate groups, improving gate concurrency per cycle. Simulations show a reduction of up to 37.44% in quantum program cycle (14.19% on average) on 53- to 127-qubit NISQ devices, with up to 1.6 × higher parallelism than state-of-the-art methods. Real-device experiments demonstrate significant acceleration in quantum computing while maintaining fidelity.
Existing quantum systems provide very limited physical qubit counts, trying to execute a quantum algorithm/circuit on them that have a higher number of logical qubits than physically available lead to a compile-time error. Given that it is unrealistic to expect existing quantum systems to provide, in near future, sufficient number of qubits that can accommodate large circuit, there is a pressing need to explore strategies that can somehow execute large circuits on small systems. In this paper, first, we perform an analysis to identify the qubits that are most suitable for circuit resizing. Our results reveal that, in most quantum programs, there exist qubits that can be reused mid-program to serially/sequentially execute the circuit employing fewer qubits. Motivated by this observation, we design, implement and evaluate a compiler-based approach that i) identifies the qubits that can be most beneficial for serial circuit execution; ii) selects those qubits to reuse at each step of execution for size minimization of the circuit; and iii) minimizes Middle Measurement (MM) delays due to impractical implementation of shots to improve the circuit reliability. Furthermore, since our approach intends to execute the circuits sequentially, the crosstalk errors can also be optimized as a result of the reduced number of concurrent gates. The experimental results indicate that our proposed approach can (i) execute large circuits that initially cannot fit into small circuits, on small quantum hardware, and (ii) can significantly improve the PST of the results by 2.1X when both original and our serialized programs can fit into the target quantum hardware.
For a specific quantum chip, multi-programming helps to improve the overall throughput and resource utilization. However, previous solutions for mapping multiple programs often lead to resource under-utilization, high error rate, and low fidelity. In this paper, we propose a new approach to map concurrent quantum programs. Our approach has three critical components. The first one is the Community Detection Assisted Partition (CDAP) algorithm, which partitions physical qubits for concurrent quantum programs by considering physical typology and the error rate, avoiding the waste of robust resources. The second one is the X-SWAP scheme that enables inter-program SWAPs and prioritizes SWAPs associated with critical gates to reduce the SWAP overheads. Finally, we propose a compilation task scheduler, which dynamically selects concurrent quantum programs to be compiled and executed together based on estimated fidelity for the best practice. We evaluate our work on publicly available quantum computer IBMQ16 and a simulated quantum chip IBMQ50. Our work outperforms the state-of-the-art work for multi-programming on fidelity and compilation overheads by 12.0% and 11.6%, respectively.
Recent advancements in quantum computing have enabled practical use of quantum error detecting and correcting codes. However, current architectures and future proposals of quantum computer design suffer from limited qubit counts, necessitating the use of high-rate codes. Such codes, with their code parameters denoted as [[n,k,d]], have more than 1 logical qubit per code (i.e., k>1). This leads to reduced error tolerance of the code, since ⌈(d−1)/2⌉ errors on any of the n physical qubits can affect the logical state of all k logical qubits. Therefore, it becomes critical to optimally map the input qubits of a quantum circuit to these codes, in such a way that the circuit fidelity is maximized. \par However, the problem of mapping program qubits to logical qubits for high-rate codes has not been studied in prior work. A brute force search to find the optimal mapping is super exponential (scaling as O(n!), where n is the number of input qubits), making exhaustive search infeasible past a small number of qubits. We propose a framework that addresses this problem on two fronts: (1) for any given mapping, it performs logical-to-physical compilation that translates input gates into efficiently encoded implementations utilizing Hadamard commutation and gate merging; and (2) it quickly searches the space of possible mappings through a merge-optimizing, noise-biased packing heuristic that identifies high-performing qubit assignments without exhaustive enumeration. To the best of our knowledge, our compiler is the first work to explore mapping and compilation for high-rate codes. Across 71 benchmark circuits, we reduce circuit depth by 34%, gate counts by up to 31% and 17% for one-qubit and two-qubit gates, and improve total variation distance by 1.75×, with logical selection rate improvements averaging 86% relative to naive compilation.