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Workshop on Quantum Networks and Distributed Quantum Computing (QuNet)

Probability-aware Qubit-to-Processor Mapping in Distributed Quantum Computing

Yingling Mao, Yu Liu, Yuanyuan Yang

Published Aug 16, 2023• 18 citations
Publisher

Abstract

Quantum computing has exciting potential but a current technological hurdle lies in the limited number of qubits in a single processor. One way to address this challenge is to assemble small, specialized quantum processors into a larger computing system, named distributed quantum computing. In this work, we focus on a key problem in distributed quantum computing: how to map logical qubits of a specific quantum circuit to different processors in a heterogeneous quantum network with the goal of minimizing the overall communication overhead. To solve this problem, we formulate a probability-aware qubit-to-processor mapping model, where the communication overhead between each pair of processors is determined through probabilistic analyses based on the link entanglement generation rates. We also introduce a multi-flow routing protocol in our model to improve the overall entanglement rates. Afterward, we employ a multistage hybrid simulated annealing algorithm to minimize the total communication overhead. Lastly, we perform extensive simulations to show the superiority of our solutions under a wide range of system settings.

DOI
10.1145/3610251.3610554

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Quantum computing has exciting potential but a current technological hurdle lies in the limited number of qubits in a single processor. One way to address this challenge is to assemble small, specialized quantum processors into a larger computing system, named distributed quantum computing. In this work, we focus on a key problem in distributed quantum computing: how to map logical qubits of a specific quantum circuit to different processors in a heterogeneous quantum network with the goal of minimizing the overall communication overhead. To solve this problem, we formulate a probability-aware qubit-to-processor mapping model, where the communication overhead between each pair of processors is determined through probabilistic analyses based on the link entanglement generation rates. We also introduce a multi-flow routing protocol in our model to improve the overall entanglement rates. Afterward, we employ a multistage hybrid simulated annealing algorithm to minimize the total communication overhead. Lastly, we perform extensive simulations to show the superiority of our solutions under a wide range of system settings.
Near-term quantum computers can hold only a small number of qubits. One way to facilitate large-scale quantum computations is through a distributed network of quantum computers. In this work, we consider the problem of distributing quantum programs represented as quantum circuits across a quantum network of heterogeneous quantum computers, in a way that minimizes the overall communication cost required to execute the distributed circuit. We consider two ways of communicating: cat-entanglement that creates linked copies of qubits across pairs of computers, and teleportation. The heterogeneous computers impose constraints on cat-entanglement and teleportation operations that can be chosen by an algorithm. We first focus on a special case that only allows cat-entanglements and not teleportations for communication. We provide a two-step heuristic for solving this specialized setting: (i) finding an assignment of qubits to computers using Tabu search, and (ii) using an iterative greedy algorithm designed for a constrained version of the set cover problem to determine cat-entanglement operations required to execute gates locally. For the general case, which allows both forms of communication, we propose two algorithms that subdivide the quantum circuit into several portions and apply the heuristic for the specialized setting on each portion. Teleportations are then used to stitch together the solutions for each portion. Finally, we simulate our algorithms on a wide range of randomly generated quantum networks and circuits, and study the properties of their results with respect to several varying parameters.
Quantum computing offers unparalleled computational capabilities but faces significant challenges, including limited qubit counts, diverse hardware topologies, and dynamic noise/error rates, which hinder scalability and reliability. Distributed quantum computing, particularly chip-to-chip connections, has emerged as a solution by interconnecting multiple processors to collaboratively execute large circuits. While hardware advancements, such as IBM's Quantum Flamingo, focus on improving inter-chip fidelity, limited research addresses efficient circuit cutting and qubit mapping in distributed systems. This project introduces DisMap, a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems. DisMap analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning, and distributed qubit mapping to minimize SWAP overhead and enhance fidelity. Implemented with IBM Qiskit and compared with the state-of-the-art, DisMap achieves up to a 20.8\% improvement in fidelity and reduces SWAP overhead by as much as 80.2\%, demonstrating scalability and effectiveness in extensive evaluations on real quantum hardware topologies.
This paper addresses the challenge of scaling quantum computing by employing distributed quantum algorithms across multiple processors. As quantum circuits grow in complexity, efficiently managing the entanglement resources required for communication between quantum processing units (QPUs) becomes increasingly critical. We propose novel methods to optimize entanglement consumption while accounting for network constraints. Our approach leverages graph partitioning techniques to optimize both qubit teleportation and gate teleportation, minimizing the number of Einstein-Podolsky-Rosen (EPR) pairs required to execute general quantum circuits. Additionally, we formulate an integer linear program (ILP) to further reduce entanglement requirements by mapping the logical resources of partitioned circuits to the physical constraints of the underlying quantum network. Finally, we analyze the entanglement cost for implementing the Quantum Fourier Transform (QFT) across multiple QPUs, employing an approach that exploits the circuit's structure to minimize total entanglement consumption. These contributions provide a pathway to scalable and resource-efficient distributed quantum computing.
When all the qubits needed for solving a problem are not located in a single quantum computer, qubits from different quantum computers can be collectively utilized. In this case, quantum communication is needed for the multiple quantum computers to communicate with each other. Several studies address the problem of minimizing the number of quantum communications when evaluating a general quantum circuit. The solutions proposed typically involve solving some intractable problems. In this paper, we show that we can obtain much better solutions when we focus on solving specific problems (instead of seeking solutions for generic circuits). Specifically, we consider several fundamental quantum circuits and identify communication protocols that need a much smaller number of communication steps than those offered by generic solutions. Our work is in line with traditional parallel and distributed computing research where typically scientists focus on solving specific problems (such as sorting, matrix multiplication, network flow, etc.) in a parallel or distributed setting.
The emerging paradigm of distributed quantum computing promises a potential solution to scaling quantum computing to currently unfeasible dimensions. While this approach itself is still in its infancy, and many obstacles must still be overcome before its physical implementation, challenges from the software and algorithmic side must also be identified and addressed. For instance, this paradigm shift requires a new form of compiler that considers the network constraints in general as well as phenomena arising due to the nature of quantum communication. In distributed quantum computing, large circuits are divided into smaller subcircuits such that they can be executed individually and simultaneously on multiple QPUs that are connected through quantum channels. As quantum communication, for example, in the form of teleportation, is expensive, it must be used sparingly. We address the problem of assigning qubits to QPUs to minimize communication costs in two different ways. First by applying time-aware algorithms that take into account the changing connectivity of a given circuit as well as the underlying network topology. We define the optimization problem, use simulated annealing and an evolutionary algorithm and compare the results to graph partitioning and sequential qubit assignment baselines. In another approach, we propose an evolutionary-based quantum circuit optimization algorithm that adjusts the circuit itself rather than the schedule to reduce the overall communication cost. We evaluate the techniques against random circuits and different network topologies. Both evolutionary algorithms outperform the baseline in terms of communication cost reduction. We give an outlook on how the approaches can be integrated into a compilation framework for distributed quantum computing.
Distributed Quantum Computing (DQC) has the potential to solve industrial large-scale problems by connecting multiple small quantum processors together to form a larger computing system. Concerning the emerging distributed paradigm, a pivotal challenge lies in crafting specialized network topologies to establish efficient connections among quantum processors while minimizing communication costs. In this paper, we propose a novel DQC topology generation algorithm (DQC-TG) to create optimal and near-optimal network topologies for homogeneous and heterogeneous quantum computers, respectively. Furthermore, for specific quantum circuits requiring diverse communication demands between each pair of qubits, we extend the original algorithm into DQC- TG- Plus to design network topologies tailored for these circuits to further enhance the performance. We perform extensive simulations to evaluate the superiority of the generated network topology designs by our algorithms to baselines.