We present the Hybrid Polar Decoder (HyPD), a hybrid of classical CMOS and quantum annealing (QA) computational structures for decoding Polar error correction codes, which are becoming widespread in today's 5G and tomorrow's 6G networks. HyPD considers CMOS for the Polar code's binary tree traversal, and QA for executing a Quantum Polar Decoder (QPD)-a novel QA-based maximum likelihood submodule. Our QPD design efficiently transforms a Polar decoder into a quadratic polynomial optimization form amenable to the QA's optimization process. We experimentally evaluate HyPD on a state-of-the-art QA device with 5,627 qubits, for Polar codes of block length 1,024 bits, in Rayleigh fading channels. Our results show that HyPD outperforms successive cancellation list decoders of list size eight by half an order of bit error rate magnitude at 1 dB SNR. Further experimental studies address QA compute time at various code rates, and with increased QA qubit numbers.
We present the Hybrid Polar Decoder (HyPD), a hybrid of classical CMOS and quantum annealing (QA) computational structures for decoding Polar error correction codes, which are becoming widespread in today's 5G and tomorrow's 6G networks. HyPD considers CMOS for the Polar code's binary tree traversal, and QA for executing a Quantum Polar Decoder (QPD)-a novel QA-based maximum likelihood submodule. Our QPD design efficiently transforms a Polar decoder into a quadratic polynomial optimization form amenable to the QA's optimization process. We experimentally evaluate HyPD on a state-of-the-art QA device with 5,627 qubits, for Polar codes of block length 1,024 bits, in Rayleigh fading channels. Our results show that HyPD outperforms successive cancellation list decoders of list size eight by half an order of bit error rate magnitude at 1 dB SNR. Further experimental studies address QA compute time at various code rates, and with increased QA qubit numbers.
We present the Hybrid Polar Decoder (HyPD), a hybrid classical-quantum decoder design for Polar error correction codes, which are becoming widespread in today’s 5G and tomorrow’s 6G networks. HyPD employs CMOS processing for the Polar decoder’s binary tree traversal, and Quantum Annealing (QA) processing for the Quantum Polar Decoder (QPD)-a Maximum-Likelihood QA-based Polar decoder submodule. QPD’s design efficiently transforms a Polar decoder into a quadratic polynomial optimization form, then maps this polynomial on to the physical QA hardware via QPD-MAP, a customized problem mapping scheme tailored to QPD. We have experimentally evaluated HyPD on a state-of-the-art QA device with 5,627 qubits, for 5G-NR Polar codes with block length of 1,024 bits, in Rayleigh fading channels. Our results show that HyPD outperforms Successive Cancellation List decoders of list size eight by half an order of bit error rate magnitude, and achieves a 1,500-bytes frame delivery rate of 99.1%, at 1 dB signal-to-noise ratio. Further studies present QA compute time considerations. We also propose QPD-HW, a novel QA hardware topology tailored for the task of decoding Polar codes. QPD-HW is sparse, flexible to code rate and block length, and may be of potential interest to the designers of tomorrow’s 6G wireless networks.
The use of quantum computation for wireless network applications is emerging as a promising paradigm to bridge the performance gap between in-practice and optimal wireless algorithms. While today's quantum technology offers limited number of qubits and low fidelity gates, application-based quantum solutions help us to understand and improve the performance of such technology even further. This paper introduces QGateD-Polar, a novel Quantum Gate-based Maximum-Likelihood Decoder design for Polar error correction codes, which are becoming widespread in today's 5G and tomorrow's NextG wireless networks. QGateD-Polar uses quantum gates to dictate the time evolution of Polar code decoding -- from the received wireless soft data to the final decoded solution -- by leveraging quantum phenomena such as superposition, entanglement, and interference, making it amenable to quantum gate-based computers. Our early results show that QGateD-Polar achieves the Maximum Likelihood performance in ideal quantum simulations, demonstrating how performance varies with noise.
Polar codes encounter challenges in decoder complexity while preserving good error-correction properties. Instead of conventional decoders, a quantum annealer (QA) decoder has been proposed to explore untapped possibilities. For future QA applications, a crucial prerequisite is transforming the optimization problem into quadratic unconstrained binary optimization (QUBO) form. However, existing QUBO forms for polar decoding result in suboptimal frame error rate (FER) performance for codes exceeding 8 bits. This paper redesigns the QUBO form for polar decoding. We first introduce a novel receiver constraint modeled by the binary cross-entropy (BCE) function. Utilizing a simulated annealing (SA) solver with the proposed QUBO form with BCE (QUBO-BCE) achieves maximum-likelihood (ML) performance for a code length of 32 bits. Next, to reduce the number of variables, we remove the frozen variables and introduce a simplified QUBO-BCE form (SQUBO-BCE). Additionally, CRC polynomials are modelled into constraints in QUBO form, resulting in a CRC-aided SQUBO-BCE (CA-SQUBO-BCE) form for polar decoding to further enhance the FER. Numerical results demonstrate that SQUBO-BCE achieves ML performance and reduces up to 61.5% of variables compared to QUBO-BCE. Furthermore, the proposed CA-SQUBO-BCE achieves near CRC-aided ML performance. The proposed SQUBO-BCE requires the lowest number of SA processes to reach a specific FER.
This paper presents an improved Ising model framework for polar codes, termed POLARIS, which reduces the number of binary variables by incorporating rate-1 node structures and embedding elements of successive-cancellation decoding into the Ising formulation. The decoder scales efficiently to block lengths up to N = 64, doubling prior Ising-based limits. POLARIS achieves near-successive-cancellation list performance within 0.4 dB while reducing QUBO dimensionality from 192 to 126 variables. These advancements bring Ising-based polar decoding closer to practical realization, offering improved efficiency for implementation on both quantum and hybrid CMOS-classical annealing hardware.
In the forthcoming 6G era, driven by the escalating demands for enhanced performance and reliability in communication systems, Low-Density Parity-Check (LDPC) codes emerge as a robust error correction coding scheme poised to effectively meet these requirements. In recent years, with the advancement of quantum computing, a proposal has emerged to integrate classical and quantum computing for the decoding of LDPC. The LDPC decoding can be treated as a Quadratic Unconstrained Binary Optimization (QUBO) problem, thereby allowing the utilization of the D-Wave 2000Q quantum annealer for solving it. Expanding on this groundwork, the paper proposes an approach to enhance quantum annealing performance using classical algorithms. Specifically, it involves performing quantum annealing on the problem first, followed by post-processed using Maximum Likelihood Estimation (MLE) for the multiple outputs, known as QAML. Furthermore, to fully exploit the advantages of quantum annealing, this paper incorporates the energy and frequency of occurrence of candidate codewords as prior information into the Maximum Likelihood Estimation. These are called QAMLE and QAMLF respectively, further enhancing decoding performance. The proposed method is evaluated and compared with direct Quantum Annealing (QA) and Quantum Annealing with post-processing using Minimum Distance (QAMD). Research findings indicate that QAML exhibits a lower bit error rate compared to QA and QAMD.
Owing to its high parallelism, belief propagation (BP) decoding is highly amenable to high-throughput implementations and thus represents a promising solution for meeting the ultra-high peak data rate of future communication systems. However, for polar codes, the error-correcting performance of BP decoding is far inferior to that of the widely used CRC-aided successive cancellation list (SCL) decoding algorithm. To close the performance gap to SCL, BP list (BPL) decoding expands the exploration of candidate codewords through multiple permuted factor graphs (PFGs). From an implementation perspective, designing a unified and flexible hardware architecture for BPL decoding that supports various PFGs and code configurations presents a big challenge. In this paper, we propose the first hardware implementation of a BPL decoder for polar codes and overcome the implementation challenge by applying a hardware-friendly algorithm that generates flexible permutations on-the-fly. First, we derive the graph selection gain and provide a sequential generation (SG) algorithm to obtain a near-optimal PFG set. We further prove that any permutation can be decomposed into a combination of multiple fixed routings, and we design a low-complexity permutation network to satisfy the decoding schedule. Our BPL decoder not only has a low decoding latency by executing the decoding and permutation generation in parallel, but also supports an arbitrary list size without any area overhead. Experimental results show that, for length-1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs has a similar error-correcting performance to SCL with a list size of 4 and achieves a throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm2 at SNR=4.0dB, which is 1.82× and 4.33× faster than the state-of-the-art BP flip and SCL decoders,~respectively