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IEEE International Conference on Application of Information and Communication Technologies (AICT)

An Improved Hybrid LDPC Decoder over Rayleigh Fading Channel

Reza Biazaran, Hermann J. Helgert

Published Oct 12, 2022• 0 citations
Publisher

Abstract

Soft decision decoders applicable to low density parity check codes such as sum product algorithms provide excellent error performance, however, it comes at the expense of computational complexity. Additionally, many iterations may be required of these decoders to achieve desired error performance. The processing delay associated with too many iterations may be a drawback for cases where low latency is a critical requirement. Conversely, performance of hard decision decoders such as bit flipping decoder and its variants, while improved, generally are not on par with that of soft decision decoders. Such decoders also require many iterations to achieve a given error performance. We have proposed a two-stage hybrid decoder with a simplified sum product algorithm (SPA) in the first stage, and an improved noisy gradient decent bit flipping decoder in the second stage. We have shown that our proposed hybrid decoder outperforms the legacy individual decoders, studied in this paper, from error performance point of view as well as required number of iterations that will reduce the overall network latency.

DOI
10.1109/aict55583.2022.10013650

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•Jan 1, 2009•1 citation
Soft decision decoders applicable to low density parity check codes such as sum product algorithms provide excellent error performance, however, it comes at the expense of computational complexity. Additionally, many iterations may be required of these decoders to achieve desired error performance. The processing delay associated with too many iterations may be a drawback for cases where low latency is a critical requirement. Conversely, performance of hard decision decoders such as bit flipping decoder and its variants, while improved, generally are not on par with that of soft decision decoders. Such decoders also require many iterations to achieve a given error performance. We have proposed a two-stage hybrid decoder with a simplified sum product algorithm (SPA) in the first stage, and an improved noisy gradient decent bit flipping decoder in the second stage. We have shown that our proposed hybrid decoder outperforms the legacy individual decoders, studied in this paper, from error performance point of view as well as required number of iterations that will reduce the overall network latency.
This paper considers a modified iterative version of the two-stage hybrid algorithm for decoding low-density parity- check (LDPC) codes. The hybrid-decision scheme is a decoding scheme used that combines two iterative decoding algorithms for decoding LDPC codes. This scheme is suitable for many applications such as audio and video transmission that are sensitive to time. The hybrid-decision scheme mixes between the characteristics of the soft-decision decoding scheme and the hard- decision decoding scheme to reduce the computational complexity of the whole decoding algorithm. The modification proposed in this paper is applied to the implementation-efficient reliability ratio weighted bit-flipping (IERRWBF) algorithm which represents hard-decision scheme in the hybrid algorithm. This modification is capable of achieving better performance than that of the hybrid decoding algorithm with reducing the number of iterations required at each SNR and approaching more to the performance of the SPA. This reduction is more observable as the maximum number of iterations assigned for the algorithm increases or as the code length increases with improving the error performance as proved by simulation results.
Gradient descent bit flipping (GDBF) and its many variants have offered remarkable improvements over legacy, or modified, bit flipping decoding techniques in case of decoding low density parity check (LDPC) codes. GDBF method and its many variants, such as noisy gradient descent bit flipping (NGDBF) have been extensively studied and their performances have been assessed over multiple channels such as binary symmetric channel (BSC), binary erasure channel (BEC) and additive white Gaussian noise (AWGN) channel. However, performance of the said decoders in more realistic channels or channel conditions have not been equally studied. An improved noisy gradient descent bit flipping algorithm is proposed in this paper that optimally decodes LDPC encoded codewords over Rayleigh fading channel and under various fade rates. Comparing to NGDBF method, our proposed decoder provides substantial improvements in both error performance of the code, and in the number of iterations required to achieve the said error performance. It subsequently reduces the end-to-end latency in applications with low or ultra-low latency requirements.
Recent advances in coding theory have uncovered the previously forgotten power of Low-Density Parity-Check (LDPC) codes. Their popularity can be related to their relatively simple iterative decoders and their potential to achieve high performance close to shannon limit. These make them an attractive candidate for error correcting application in communication systems. In this thesis, we focus our research on the iterative decoding algorithms for Low-Density Parity-Check codes and present an improved decoding algorithm. First, the graph structure of LDPC codes is studied and a graph-based search algorithm to find the shortest closed walk and shortest cycle for each node of the graph is proposed. Then, the Deterministic schedule is applied on nodes of the graph with the objective of preserving the optimality of the algorithms. Finally, Hybrid Switch-Type technique is applied on the improved algorithms to provide a desirable complexity/performance trade-off. Hybrid Technique and Deterministic schedule are combined for decoding regular and irregular LDPC codes. The performance and complexity of the decoder is studied for Sum-Product and Gallager A algorithms. The result is a flexible decoder for any available LDPC code and any combination of decoding algorithms based on the communication systems need. In this technique, we benefit the high performance of soft-decision algorithms and low complexity of hard-decision algorithms by changing the decoding rule after a few iterations. Hence, a desirable performance can be obtained with less average number of soft iterations. Moreover, all the nodes do not update messages in each iteration. As a result, the total number of computations is reduced considerably
Low Density Parity Check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. In many digital communication systems, these codes have strong competitors of turbo codes for error control. LDPC codes performance depends on the excellent design of parity check matrix and many diverse research methods have been used by different study groups to evaluate the performance. Unlike many other classes of codes, LDPC codes are already equipped with a fast, probabilistic decoding algorithm. This makes LDPC codes not only attractive from a theoretical point of view, but also very suitable for practical applications. This paper throws hard decision and soft decision algorithm of LDPC. The hard decision algorithm contains Bit flipping algorithm and Soft decoding algorithm contains Sum product algorithm which is used to correct burst error. Sum Product algorithm is also called as belief propagation. Bit flipping and Sum Product algorithms are explained and can be implemented for the generated parity check matrix of (1016x508) for LDPC code with code rate 1/2.
Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren't real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.
Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, withuncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound. In this thesis, a modification to the sum-product decoding algorithm called early-decision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sum-product decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains. The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization andenergy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.