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International Multi-Conference on Systems, Signals & Devices (SSD)

Performance Evaluation of Bit-Flipping Based Algorithms for LDPC Convolutional Codes

Oulfa Laouar, Imed Amamra, Nadir Derouiche

Published May 6, 2022• 4 citations
Publisher
DOI
10.1109/ssd54932.2022.9955830

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IEEE Transactions on Circuits and Systems I Regular Papers•May 1, 2010•12 citations
A new class of iterative bit flipping (BF) decoding algorithms adapted for low-density parity check (LDPC) convolutional codes is proposed. Compared with Gallager's original BF algorithm, the new BF algorithms improve both the coding gain and the error correction speed. At a bit error rate (BER) of 10 , the best of the new bit-flipping algorithms achieves, after only 6 iterations and with much simpler decoding hardware, a coding gain within 3.5 dB of that of the conventional min-sum belief propagation decoding algorithm.
In this paper, we present three construction methods of systematic regular LDPC-CCs based on randomly or algebraically structured sparse matrices. We provide an overview of LDPC-CCs and compares between Gallager’s, Mackay-Neal and Quasi-Cyclic (QC) construction methods, which are a good choice for many wireless applications due to their errors correction efficiency and low decoding complexity. At a rate-1/2, for the same size of the parity matrix to obtain the same encoding and decoding complexity, and using the Bit Flipping (BF) decoding algorithm over Additive White Gaussian Noise (AWGN) channel, we simulated the BER performance of a (3,6) regular LDPC convolutional codes, where the results showed that Gallager’s construction method (random) outperforms Mackay-Neal and QC ones.
VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.