Along with the recent development of quantum computers, quantum computer simulators are also exploited to verify and evaluate quantum computers. Since the amount of computation in the quantum circuit simulations increases exponentially with the number of qubits, which indicates the size of the quantum computer, it is important to study the performance of the quantum circuit simulations. In this paper, we analyze the performance of a state vector quantum circuit simulation on A64FX processor. We consider the implementation with the optimization control lines (OCLs), and that written with the Arm C Language Extensions (ACLE) to enhance vectorization, and compare them with the original implementation. Our experiments show that the vectorization improves the performance if the quantum gate simulations involve floating-point arithmetic operations.
Along with the recent development of quantum computers, quantum computer simulators are also exploited to verify and evaluate quantum computers. Since the amount of computation in the quantum circuit simulations increases exponentially with the number of qubits, which indicates the size of the quantum computer, it is important to study the performance of the quantum circuit simulations. In this paper, we analyze the performance of a state vector quantum circuit simulation on A64FX processor. We consider the implementation with the optimization control lines (OCLs), and that written with the Arm C Language Extensions (ACLE) to enhance vectorization, and compare them with the original implementation. Our experiments show that the vectorization improves the performance if the quantum gate simulations involve floating-point arithmetic operations.
ARM SVE and RISC-V RVV are emerging vector architectures in high-end processors that support vectorization of flexible vector length. In this work, we leverage an important workload for quantum computing, quantum state-vector simulations, to understand whether high-performance portability can be achieved in a vector-length agnostic (VLA) design. We propose a VLA design and optimization techniques critical for achieving high performance, including VLEN-adaptive memory layout adjustment, load buffering, fine-grained loop control, and gate fusion-based arithmetic intensity adaptation. We provide an implementation in Google's Qsim and evaluate five quantum circuits of up to 36 qubits on three ARM processors, including NVIDIA Grace, AWS Graviton3, and Fujitsu A64FX. By defining new metrics and PMU events to quantify vectorization activities, we draw generic insights for future VLA designs. Our single-source implementation of VLA quantum simulations achieves up to 4.5x speedup on A64FX, 2.5x speedup on Grace, and 1.5x speedup on Graviton.
The state vector-based simulation offers a convenient approach to developing and validating quantum algorithms with noise-free results. However, limited by the absence of cache-aware implementations and unpolished circuit optimizations, the past simulators were severely constrained in performance, leading to stagnation in quantum computing. In this paper, we present an innovative quantum circuit simulation toolkit comprising gate optimization and simulation modules to address these performance challenges. For the performance, scalability, and comprehensive evaluation, we conduct a series of particular circuit benchmarks and strong scaling tests on a DGX-A100 workstation and achieve averaging 9 times speedup compared to state-of-the-art simulators, including QuEST, IBM-Aer, and NVIDIA-cuQuantum. Moreover, the critical performance metric FLOPS increases by up to a factor of 8-fold, and arithmetic intensity experiences a remarkable 96x enhancement. We believe the proposed toolkit paves the way for faster quantum circuit simulations, thereby facilitating the development of novel quantum algorithms.
Quantum computer simulators running on classical computers are essential for developing real quantum computers and emerging quantum applications. In particular, state vector simulators, which store a full state vector in memory and update it in every quantum operation, can be used to simulate an arbitrary form of quantum circuits, debug quantum applications, and validate future quantum computers. Since the time and space complexity grows exponentially with the number of qubits and easily exceeds the capability of a single machine, various distributed state vector simulators are developed. However, these are tuned for common CPUs and GPUs, not for ARM CPUs. Therefore, we develop a distributed state vector simulator, mpiQulacs, that is optimized for large-scale simulation on A64FX-based cluster systems. A64FX is a 48-core ARM-based CPU having high-bandwidth memory (HBM2) and also used in one of the world's top supercomputers, Fugaku. As computational optimization, we vectorize qubit operations with Scalable Vector Extension (SVE) to fully utilize its HBM2. To reduce the amount of inter-node communication for scalable simulation, mpiQulacs provides a fused-swap gate that collectively performs multiple swap operations as one operation and a quantum circuit optimizer that automatically adds fused-swap gates to a circuit. We evaluate weak and strong scaling of mpiQulacs with up to 39 qubits on our 512-node A64FX-based cluster system. The result shows that mpiQulacs achieves high-scalability on hundreds of nodes in benchmark and practical quantum circuits, and its performance is comparable with the existing well-known distributed state vector simulators.
Quantum-mechanical phenomena are playing an increasing role in information processing as transistor sizes approach the nanometer level, while the securest forms of communication rely on quantum data encoding. When they involve a finite number of basis states, these phenomena can be modeled as quantum circuits, the quantum analogue of conventional or classical logic circuits. Simulation of quantum circuits can therefore be used as a tool to evaluate issues in the design of quantum information processors. Unfortunately, simulating such phenomena efficiently is exceedingly difficult. The matrices representing quantum operators (gates) and vectors modeling quantum states grow exponentially with the number of quantum bits. The information represented by quantum states and operators often exhibits structure that can be exploited when simulating certain classes of quantum circuits. We study the development of simulation methods that run on classical computers and take advantage of such repetitions and redundancies. In particular, we define a new data structure for simulating quantum circuits called the quantum information decision diagram (QuIDD). A QuIDD is a compressed graph representation of a vector or matrix and permits computations to be performed directly on the compressed data. We develop a comprehensive set of algorithms for operating on QuIDDs in both the state-vector and density-matrix formats, and evaluate their complexity. These algorithms have been implemented in a general-purpose simulator program for quantum-mechanical applications called QuIDDPro. Through extensive experiments conducted on representative quantum simulation applications, including Grover's search algorithm, error characterization, and reversible circuits, we demonstrate that QuIDDPro is faster than other existing quantum-mechanical simulators such as the National Institute of Standards and Technology's QCSim program, and is far more memory-efficient. Using QuIDDPro, we explore the advantages of quantum computation over classical computation, simulate quantum errors and error correction, and study the impact of numerical precision on the fidelity of simulations. We also develop several novel algorithms for testing quantum circuit equivalence and compare them empirically. The QuIDDPro software is equipped with a user-friendly interface and is distributed with numerous example scripts. It has been used as a laboratory supplement for quantum computing courses at several universities.
State-of-the-art quantum circuit simulators have mostly focused on scaling the number of qubits. However, we argue that studying current noisy quantum computers and variational quantum algorithms benefits from high-throughput simulation of intermediate-scale quantum circuits. We present the first implementation and evaluation of a batched quantum simulator on the NEC Vector Engine (VE), a vector processor with massive memory bandwidth that is ideal for memory-intensive state vector simulation. To take advantage of the long-vector architecture of VE, we design a parallelization strategy and memory layout suited for batched state vector simulation. Our evaluation shows that the latest-generation VE Type 30A achieves equal performance as the NVIDIA A100 80 GB model for single-qubit gates, but slightly underperforms A100 for two-qubit gates. Furthermore, our vector-friendly noise gate implementation offers a large speedup compared to that of cuStateVec. When simulating a noisy 16-qubit random circuit with our simulator, VE30 is up to 1.95 × faster than A100.
Advances in quantum simulator technology are increasingly required because research on quantum algorithms is becoming more sophisticated and complex. State vector simulation utilizes CPU and memory resources in computing nodes exponentially with respect to the number of qubits; furthermore, in a variational quantum algorithm, the large number of repeated runs by classical optimization is also a heavy load. This problem has been addressed by preparing numerous computing nodes or simulation frameworks that operate effectively. This study aimed to accelerate quantum simulation using two newly proposed methods: to efficiently utilize limited computational resources by adjusting the ratio of the MPI and distributed processing parallelism corresponding to the target problem settings and to slim down the Hamiltonian by considering the effect of accuracy on the calculation result. Ground-state energy calculations of a fermionic model were performed using a variational quantum eigensolver (VQE) on an HPC cluster with up to 1024 FUJITSU Processor A64FX connected to each other by InfiniBand; the processor is also used on supercomputer Fugaku. We achieved 200 times higher speed over VQE simulations and demonstrated 32 qubits ground-state energy calculations in acceptable time. This result indicates that > 30 qubit state vector simulations can be realistically utilized for further research on variational quantum algorithms.