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Testbed capabilities to catalyze NISQ processor applications.

Mohan Sarovar

Published Dec 1, 2021• 0 citations
Publisher

Abstract

for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.
DOI
10.2172/1901834

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Quantum volume (QV) has become the de-facto standard benchmark to quantify the capability of Noisy Intermediate-Scale Quantum (NISQ) devices. While QV values are often reported by NISQ providers for their systems, we perform our own series of QV calculations on 24 NISQ devices currently offered by IBM Q, IonQ, Rigetti, Oxford Quantum Circuits, and Quantinuum (formerly Honeywell). Our approach characterizes the performances that an advanced user of these NISQ devices can expect to achieve with a reasonable amount of optimization, but without white-box access to the device. In particular, we compile QV circuits to standard gate sets of the vendor using compiler optimization routines where available, and we perform experiments across different qubit subsets. We find that running QV tests requires very significant compilation cycles, QV values achieved in our tests typically lag behind officially reported results and also depend significantly on the classical compilation effort invested.
In recent years, Quantum Computing (QC) has progressed to the point where small working prototypes are available for use. Termed Noisy Intermediate-Scale Quantum (NISQ) computers, these prototypes are too small for large benchmarks or even for Quantum Error Correction (QEC), but they do have sufficient resources to run small benchmarks, particularly if compiled with optimizations to make use of scarce qubits and limited operation counts and coherence times. QC has not yet, however, settled on a particular preferred device implementation technology, and indeed different NISQ prototypes implement qubits with very different physical approaches and therefore widely-varying device and machine characteristics.
The benchmark of Noisy Intermediate-Scale Quantum (NISQ) computers plays a major role in the research and development of quantum devices and algorithms. Our study aims to investigate a single metric of benchmarking for the Noisy Intermediate-Scale Quantum device. We use state-of-the-art applications to generate a device-score according to our proposed formula. Our study utilizes Quantum Volume (QV) to determine the qubit circuit size for each device. Furthermore, we utilize SupermarQ to determine each application's benchmark score, utilizing their 5 feature vectors to indicate the circuit performance, and applying their circuit optimization techniques to configure the transpiler. Our experiment shows that device-score of the simulated IBM backend are directly correlated to Quantum Volume. However, it should be noted that topology and gate error are also embedded in the benchmark scores of the applications. Because of this, our study introduces the device-score, a single number metric that provides a more precise scale with the assistance of Quantum Volume and SupermarQ.