The present paper shows possible ways to design monolithic Quantum Random Number Generators (QRNGs) in a standard CMOS technology. While all commercial QRNGs based on SPAD technology use an external light as main source of entropy, in the present implementation silicon-based photon sources are used. This approach allows the integration of monolithic QRNGs paving the way towards miniaturized and low-cost devices. Moreover, being the QRNG realized in a standard CMOS technology, in perspective, it can potentially be embedded in secure microprocessor. In the paper we show that the proposed approach is compact, produces a minimum event rate of about 1kHz, possibly extended in case of the implementation of multi-QRNGs working in parallel.
The present paper shows possible ways to design monolithic Quantum Random Number Generators (QRNGs) in a standard CMOS technology. While all commercial QRNGs based on SPAD technology use an external light as main source of entropy, in the present implementation silicon-based photon sources are used. This approach allows the integration of monolithic QRNGs paving the way towards miniaturized and low-cost devices. Moreover, being the QRNG realized in a standard CMOS technology, in perspective, it can potentially be embedded in secure microprocessor. In the paper we show that the proposed approach is compact, produces a minimum event rate of about 1kHz, possibly extended in case of the implementation of multi-QRNGs working in parallel.
A compact quantum random number generator (QRNG) based on an array of Single Photon Avalanche Diodes (SPADs) is presented here. The main feature of the proposed chip is the capability to generate random numbers without the use of any external source of light. In this view, SPADs are configured to be used in two ways: 1) as a controlled light emitter and 2) as a detector. An embedded logic is able to distinguish dark events against detected emitted photon in such a way to make the system sensitive only to the presence of light. The extracted random bits show a uniform distribution and the QRNG, thanks to an integrated conditioning block maximizing the output entropy, eventually passes all AIS31 tests. The average raw bit rate in the default device configuration (one enabled column) is measured equal to 800 kbps.
A compact quantum random number generator based on an array of Single Photon Avalanche Diode (SP AD) is presented here. As the main feature, the proposed chip has the capability to generate random numbers without the use of an external source of light. In the present approach, SP AD devices are used as emitters and as detectors. An embedded logic allows distinguishing dark events from events coming from the photon emission. The extracted random bit sequence shows a quite uniform distribution and after being post-processed by means of an integrated circuit, used to maximize the entropy of the system, is able to pass the AIS31 test. The average bit rate is 400 kbps.
Quantum random number generators (QRNGs) leverage the inherent unpredictability of quantum mechanical phenomena to produce random numbers. However, the performance of many QRNGs is hindered by limitations such as low generation rates and the bulkiness of systems utilizing single-photon detectors (SPDs). In this study, we present a QRNG that addresses these challenges by using a micro-LED as an entropy source, utilizing the intensity fluctuations of spontaneous emissions. By applying post-processing techniques, our 5 × 5 µm 2 micro-LED-based system achieves a PD bandwidth-limited generation rate of 9.375 Gbit/s while successfully passing the required randomness tests outlined by the National Institute of Standards and Technology (NIST). Importantly, systematic testing across micro-LEDs of varying sizes demonstrates consistently high performance, highlighting the robustness of this approach. The compact, small footprint, scalable design, and surface emission characteristics of micro-LEDs pave the way for the development of parallel QRNG-integrated chips, which hold the potential to deliver ultra-high random number generation rates in practical, miniaturized platforms.
In today's digital life, security and encryption are becoming more and more important. As random number generators are a fundamental block of security and encryption, it is crucial to guarantee that these devices operate securely. Random numbers are usually generated in two ways; pseudo random number generators (PRNGs) and true random random number generators (TRNGs). PRNGs output a sequence based on a seed and a mathematical function. The deterministic nature of pseudo RNG devices can result in the PRNG not being applicable for all protocols, in which case TRNGs are needed. Almost all strong cryptography requires TRNGs to generate keys. The difference is that these devices instead rely on real world physics in order to generate a random number. The TRNG implementation explored in this thesis makes use of the quantum mechanical properties of photons. TRNGs making use of this principle of elementary quantum mechanical decision making are called quantum random number generators (QRNGs). This source of entropy provided by photons can be extracted by utilizing SPADs. QRNG devices based on SPADs have been made before in different ways, however there are still large grounds undiscovered when concerning SPAD based designs. As SPAD based QRNGs can be completely produced using CMOS technology, a world of possibilities open, including integration with already existing designs. Different aspects of SPAD QRNG designs will be discussed in this thesis; size, speed, hybrid designs and QRNG test-benching. The first part of the exploration focuses on creating an as small as possible QRNG. This resulted in a QRNG design which is as small as just one flip-flop and one SPAD, which is the smallest QRNG at the time of writing to the authors knowledge. Simulations show that the device is able to run up to 25 Mb/s using a SPAD with low deadtime. This device has been produced using 140nm technology by STMicroelectronics. The second part of the exploration, delves into how fast a SPAD based QRNG can be. The main goals here were to make the fastest possible QRNG with good scalability characteristics. This resulted in a design proposition based on the difference in the time of flight of two photons. This design is simulated using Matlab, and can reach 70 Mb/s per SPAD-duo depending on the deadtime of the SPAD used. When using a SPAD with a deadtime of 1us, the scaled up design needs only 16% of the SPADS needed by a state-of-the-art SPAD based QRNG design based on simulations. The amount of SPADs needed however schales almost linearly with a lower deadtime, having the potential to need only a fraction of the SPADs needed by the state-of-the-art in order to reach the same speeds. Then the concept of hybrid devices is explored, making use of a combination of PRNG and QRNG systems. The first hybrid design proposed is a design in which a very small QRNG is used to generate the key for multiple secure PRNG systems. The PRNG system used in this design is a trivium stream cypher. The design is completely written in VHDL except for the external QRNG. It then has been compiled and simulated using ModelSim, again using 140nm technology by STMicroelectronics. This resulted in a design which is able to reach speeds of 640 Gb/s, while using a total area of 99936 um2. The second hybrid device proposes a LFSR based design, which makes use of multiple very small QRNG devices to influence the function that the LFSR implements in order to increase the security. The last part of the exploration explores how it can be made easier and faster to test QRNG designs in an early design stage more accurately. As the source of entropy is quantum, the only risk of affecting the randomness is purely in which form the data of the photons is processed. By creating a chip which is able to extract the time of flight and the exact location of where the photon hit, testing potential QRNG devices can already be done in an early design stage with real-time data. A part of the chip that measures the time of flight of the photons arriving, has been designed in 40nm technology by STMicroelectronics. This part is a novel counter based on the principle of Gray counting, and is simulated extensively using extracted layout simulations. These simulations show that the device is able to run at speeds up to 3.6 GHz.
Abstract Random numbers play a crucial role in numerous scientific applications. Source-independent quantum random number generators (SI-QRNGs) can offer true randomness by leveraging the fundamental principles of quantum mechanics, eliminating the need for a trusted source. Silicon photonics shows great promise for QRNG due to its benefits in miniaturization, cost-effective device manufacturing, and compatibility with CMOS microelectronics. In this study, we experimentally demonstrate a silicon-based discrete variable SI-QRNG. Using a well-calibrated chip and an optimized parameter strategy, we have achieved the highest quantum random number generation rate of 7.9 Mbits/s. Our research paves the way for integrated SI-QRNGs.
The security of electronic devices has become a key requisite for the rapidly-expanding pervasive and hyper-connected world. Robust security protocols ensuring secure communication, device's resilience to attacks, authentication control and users privacy need to be implemented. Random Number Generators (RNGs) are the fundamental primitive in most secure protocols but, often, also the weakest one. Establishing security in billions of devices requires high quality random data generated at a sufficiently high throughput. On the other hand, the RNG should exhibit a high integration level with on-chip extraction to remove, in real time, potential imperfections. We present the first integrated Quantum RNG (QRNG) in a standard CMOS technology node. The QRNG is based on a parallel array of independent Single-Photon Avalanche Diodes (SPADs), homogeneously illuminated by a DC-biased LED, and co-integrated logic circuits for postprocessing. We describe the randomness generation process and we prove the quantum origin of entropy. We show that co-integration of combinational logic, even of high complexity, does not affect the quality of randomness. Our CMOS QRNG can reach up to 400 Mbit/s throughput with low power consumption. Thanks to the use of standard CMOS technology and a modular architecture, our QRNG is suitable for a highly scalable solution.