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International Journal of Advance Engineering and Research Development

QUANTUM CIRCUIT OPTIMIZATION (FOR 3 QUBITS)

Published Jun 30, 2015• 0 citations
Publisher
DOI
10.21090/ijaerd.020643

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AbstractA brief review is given of possible Finsler metrics de ned on the SU (2 n )group tangent bundle which may be suitable for quantum circuit optimiza-tion. 1 INTRODUCTION In the Riemannian geometry of quantum computation, a Riemannian hasbeen exploited for the purpose of quantum circuit optimization [1]-[4]. Finslermetrics are a more general class of metrics of which Riemannian metrics area special case based on a quadratic form [5]-[8]. A Finsler need not bequadratic. In fact Bernard Riemann was the rst to consider a basedon a quartic form [9], but he settled on a quadratic form because of its greatersimplicity. Much later, Paul Finsler introduced Finsler geometry in his thesis[10]. The purpose of the present work is to brie‡y review possible Finsler metricsfor quantum circuit optimization [11],[1] . 2 QUANTUM CIRCUIT OPTIMIZATION For a manifold M with a so-called local metric [11], there is a function F (x;y )of coordinates x on M and y on the tangent space manifold TM . One requiresF (x;y ) = 0 for xed x, and F (x;y ) is vanishing for y = 0. F (x;y ) is positivelyhomogeneous of degree 1 in y , namely,F (x;y ) = F (x;y );  > 0; (1)and satis es the triangle inequality in the tangent space variable y , namely,F (x;y
During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to find critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.