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International Multi-Symposiums on Computer and Computational Sciences

Novel Efficient Check Node Update Implementations for Row Weight Matched Min-Sum Algorithm

Xin Lu, Jun Xu

Published Aug 1, 2007• 0 citations
Publisher

Abstract

This paper has presented various Min-Sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. For one check node update of Normalized Min-Sum algorithm, if the current row weight is dc, dc multiplications are needed. If dc is large, dc multiplications are needed, which leads to high complexity. In this article, one innovative method for check node update has been found, which can obviously reduce the number of comparison/selection operations for the row weight matched Min-Sum algorithm of high rate LDPC codes. Simulations have claimed the performance of row weight matched Min-Sum is nearly the same as that of Log-BP, namely the optimal algorithm, which has shown that row weight matched Min-Sum are good choices for LDPC decoding.

DOI
10.1109/imsccs.2007.4392663

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This paper has presented various Min-Sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. For one check node update of Normalized Min-Sum algorithm, if the current row weight is dc, dc multiplications are needed. If dc is large, dc multiplications are needed, which leads to high complexity. In this article, one innovative method for check node update has been found, which can obviously reduce the number of comparison/selection operations for the row weight matched Min-Sum algorithm of high rate LDPC codes. Simulations have claimed the performance of row weight matched Min-Sum is nearly the same as that of Log-BP, namely the optimal algorithm, which has shown that row weight matched Min-Sum are good choices for LDPC decoding.
This paper has presented various Min-Sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. For one check node update of Normalized Min-Sum algorithm, if the current row weight is dc, dc multiplications are needed. If dc is large, dc multiplications are needed, which leads to high complexity. In this article, one innovative method for check node update has been found, which can obviously reduce the number of comparison/selection operations for the row weight matched Min-Sum algorithm of high rate LDPC codes. Simulations have claimed the performance of row weight matched Min-Sum is nearly the same as that of Log-BP, namely the optimal algorithm, which has shown that row weight matched Min-Sum are good choices for LDPC decoding.
This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. For one check node update of normalized min-sum algorithm, if the current row weight is dc, dcmultiplications are needed. If dcis large, dcmultiplications are needed, which leads to high complexity. In this article, one innovative method for check node update has been found, which can obviously reduce the number of multiplication operations for the normalized min-sum algorithm and the number of comparison/selection operations for the row weight matched min-sum algorithm of high rate LDPC codes. Simulations have claimed the performance of normalized min-sum and row weight matched min-sum is nearly the same as that of Log-BP, namely the optimal algorithm, which has shown that normalized min-sum and row weight matched min-sum are good choices for LDPC.
This paper presents various Min-Sum-related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation.For one check node update of Normalized Min-Sum algorithm(Nor-MS),if the current row weight is d c,d cmultiplications are needed.If d cis large,this would lead to high complexity.An innovative method for check node update is proposed,which could obviously reduce the number of multiplication operations for the Nor-MS algorithm and the number of comparison/selection operations for the Rwm-MS algorithm of high rate LDPC codes.Simulations indicate that the performance of Nor-MS and Rwm-MS is almost the same as that of Log-BP,namely the optimal algorithm,and that Nor-MS and Rwm-MS are good choices for LDPC decoding.
This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. The m-to-2m decoder has been introduced to generate more efficient new hardware implementations of check node update, which can obviously reduce the number of multiplication operations for normalized min-sum algorithm for high rate LDPC codes. Simulations have claimed the performance of normalized min-sum is nearly the same as that of Log-BP, namely the optimal algorithm. In general, this paper has proved that normalized min-sum is good choices as LDPC decoding methods.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1
In this paper, the partial-min algorithms are proposed for updating the check node messages in decoding low-density parity-check (LDPC) codes. The proposed methods can achieve a good performance-versus-complexity tradeoff by reducing both the check node processor complexity and the decoder memory requirements. Float-point and fixed-point simulation results show that a near optimum performance can be maintained. The architecture of a check node processor implementing the partial-min algorithms is also presented. The hardware expense especially the memory requirement is analyzed and compared with normal decoding architectures