The Google Quantum AI team's long-term goal is to realize a large-scale fault-tolerant quantum computer. Of the technologies available to implement the quantum processor at the core of such a system, solid-state superconducting circuits based on Josephson junctions (JJs) are among the strongest contenders. Recent demonstrations with this technology include computation beyond the capabilities of today's most powerful supercomputers [1] and execution of quantum error correction (QEC) codes that can detect and correct either bit or phase flip errors [2]. These exciting results were enabled by low-error-rate quantum processors with tens of qubits and the supporting infrastructure to run these devices. However, today's quantum computers still have orders of magnitude fewer qubits than is required for a useful fault-tolerant quantum computer; for this, an estimated million or more qubits will be needed and scaling-up today's technology to this extent is non-trivial. Here, we review the Google Quantum AI team's recent progress and future plans. Specifically, we describe our post-classical Sycamore quantum computer and discuss the Google Quantum AI roadmap to fault-tolerant quantum computing.
The Google Quantum AI team's long-term goal is to realize a large-scale fault-tolerant quantum computer. Of the technologies available to implement the quantum processor at the core of such a system, solid-state superconducting circuits based on Josephson junctions (JJs) are among the strongest contenders. Recent demonstrations with this technology include computation beyond the capabilities of today's most powerful supercomputers [1] and execution of quantum error correction (QEC) codes that can detect and correct either bit or phase flip errors [2]. These exciting results were enabled by low-error-rate quantum processors with tens of qubits and the supporting infrastructure to run these devices. However, today's quantum computers still have orders of magnitude fewer qubits than is required for a useful fault-tolerant quantum computer; for this, an estimated million or more qubits will be needed and scaling-up today's technology to this extent is non-trivial. Here, we review the Google Quantum AI team's recent progress and future plans. Specifically, we describe our post-classical Sycamore quantum computer and discuss the Google Quantum AI roadmap to fault-tolerant quantum computing.
With quantum computing’s potential to solve classically insurmountable problems, quantum computation has emerged as a transformative paradigm across various fields such as cryptography, materials science, and artificial intelligence. The pursuit of scalable and fault-tolerant quantum computation is at the heart of this evolution. The examination examines the evolution of quantum computing architectures, such as superconducting qubits and quantum error correction (QEC) codes until the recent advancement in Google’s Willow processor. This review highlights this progression. We examine the development of Noisy Intermediate-Scale Quantum (NISQ) devices and the first instances of below-threshold QEC, where an increase in qubit count leads to exponentially lower error rates. By using Willow’s 105-qubit architecture, it is possible to perform real-time error correction on a 77 logical qubit grid and complete random circuit sampling in under five minutes, which would otherwise be an insurmountable task. We examine the way Willow’s method is compared to other quantum platforms and discuss its potential impact on early fault-tolerant quantum computing (EFTQC), scalability, and the future of intelligent quantum systems. In conclusion, the paper highlights some of the open issues and opportunities in quantum hardware, artificial intelligence (AI), and fault-tolerant computation.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.
Abstract: The rapid advancement of quantum computing is largely driven by innovations in quantum chip architectures, with superconducting and topological qubits emerging as the most promising candidates for scalable and fault-tolerant quantum processors. Superconducting qubits, built using Josephson junctions, have demonstrated significant progress in coherence time, gate fidelity, and quantum error correction, making them the backbone of leading quantum processors such as IBM’s Eagle and Google’s Sycamore. Meanwhile, topological qubits, based on Majorana zero modes (MZMs) and non-Abelian anyons, offer intrinsic error resistance, reducing the computational overhead required for fault-tolerant quantum operations. This chapter explores the fundamental principles, fabrication techniques, and scalability challenges associated with these next-generation quantum chips, highlighting key advancements in hybrid quantum architectures, quantum error mitigation, and cryogenic quantum-classical interfacing. Additionally, it examines the geopolitical and ethical considerations of quantum supremacy, along with the transformative impact of next-gen quantum chips on AI, cryptography, materials science, and optimization problems. As research accelerates, the path toward scalable, fault-tolerant quantum computing is becoming clearer, paving the way for a future where quantum processors outperform classical supercomputers in solving the world’s most complex challenges. Keywords: Quantum chips, superconducting qubits, topological qubits, Josephson junctions, Majorana zero modes, quantum error correction, hybrid quantum architectures, fault-tolerant quantum computing, cryogenic electronics, quantum-classical interfacing, scalable quantum processors, AI-driven quantum computing, quantum supremacy, post-quantum cryptography, nanofabrication, quantum hardware innovation
Quantum processing units (QPUs) built on superconducting Josephson junctions remain the most industrially mature route to fault-tolerant quantum computing, but the field has moved substantially since early 2025. This paper provides an updated overview of Josephson-junction QPUs, grounded in the quantum-mechanical principles, superposition, entanglement, and decoherence, that any qubit implementation must contend with, and in the physics of Cooper pairing and quantum tunneling that make a Josephson junction behave as a controllable qubit. We examine the engineering challenges of scaling these devices, including crosstalk, classical control-interface bottlenecks, and quantum error correction, and discuss the first below-threshold surface-code demonstrations on superconducting hardware. We survey recent materials advances, near-term computational results, and applications beyond computing, and compare Josephson-junction QPUs against trapped-ion, photonic, and neutral-atom alternatives, the latter having emerged as a serious fourth architecture since our original analysis. We close with the current public roadmaps toward fault-tolerant superconducting quantum computers and a calibrated assessment of how much progress those roadmaps still require.
By using a superconducting processor, Google Quantum AI group demonstrated that a logic qubit realized by surface code of quantum error correction performs better when the number of physical qubits increases. Two surface codes to encode logic qubits for scaling are realized experimentally, with multiple cycles of quantum error correcting assisted by ancillary qubits. This result can be considered as an important step toward fault-tolerant quantum computers. In this review paper, we introduce briefly the mechanism of quantum error correction. As an example, Shor’s nine-qubit error correction code is explained. Then, the new experiments of Google quantum AI group are introduced to show their significance in scaling. The advances in other quantum error correction experiments are also reviewed. Finally, the development of quantum computers is discussed.