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International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators

Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Darren Lyles, George Michelogiannakis

Published Feb 22, 2022• 18 citations
Publisher

Abstract

Superconducting technology is a prime candidate for the future of computing. However, current superconducting prototypes are limited to small-scale examples due to stringent area constraints and complex architectures inspired from voltage-level encoding in CMOS; this is at odds with the ps-wide Single Quantum Flux (SFQ) pulses used in superconductors to carry information. In this work, we propose a wave-pipelined Unary SFQ (U-SFQ) architecture that leverages the advantages of two data representations: pulse-streams and Race Logic (RL). We introduce novel building blocks such as multipliers, adders, and memory cells, which leverage the natural properties of SFQ pulses to mitigate area constraints. We then design and simulate three popular hardware accelerators: i) a Processing Element (PE), typically used in spatial architectures; ii) A dot-product-unit (DPU), one of the most popular accelerators in artificial neural networks and digital signal processing (DSP); and iii) A Finite Impulse Response (FIR) filter, a popular and computationally demanding DSP accelerator. The proposed U-SFQ building blocks require up to 200× fewer JJs compared to their SFQ binary counterparts, exposing an area-delay trade-off. This work mitigates the stringent area constraints of superconducting technology.

DOI
10.1145/3503222.3507765

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Superconducting technology is a prime candidate for the future of computing. However, current superconducting prototypes are limited to small-scale examples due to stringent area constraints and complex architectures inspired from voltage-level encoding in CMOS; this is at odds with the ps-wide Single Quantum Flux (SFQ) pulses used in superconductors to carry information. In this work, we propose a wave-pipelined Unary SFQ (U-SFQ) architecture that leverages the advantages of two data representations: pulse-streams and Race Logic (RL). We introduce novel building blocks such as multipliers, adders, and memory cells, which leverage the natural properties of SFQ pulses to mitigate area constraints. We then design and simulate three popular hardware accelerators: i) a Processing Element (PE), typically used in spatial architectures; ii) A dot-product-unit (DPU), one of the most popular accelerators in artificial neural networks and digital signal processing (DSP); and iii) A Finite Impulse Response (FIR) filter, a popular and computationally demanding DSP accelerator. The proposed U-SFQ building blocks require up to 200× fewer JJs compared to their SFQ binary counterparts, exposing an area-delay trade-off. This work mitigates the stringent area constraints of superconducting technology.
Most popular superconducting circuits operate on information carried by ps-wide, μV-tall, single flux quantum (SFQ) pulses. These circuits can operate at frequencies of hundreds of GHz with orders of magnitude lower switching energy than complementary-metal-oxide-semiconductors (CMOS). However, under the stringent area constraints of modern superconductor technologies, fully-fledged, CMOS-inspired superconducting architectures cannot be fabricated at large scales. Unary SFQ (U-SFQ) is an alternative computing paradigm that can address these area constraints. In U-SFQ, information is mapped to a combination of streams of SFQ pulses and in the temporal domain. In this work, we extend U-SFQ to introduce novel building blocks such as a multiplier and an accumulator. These blocks reduce area and power consumption by 2 ×\times× and 4 ×\times× compared with previously proposed U-SFQ building blocks and yield at least 97% area savings compared with binary approaches. Using these multiplier and adder, we propose a U-SFQ Convolutional Neural Network (CNN) hardware accelerator capable of comparable peak performance with state-of-the-art superconducting binary approach (B-SFQ) in 32 ×\times× less area. CNNs can operate with 5–8 bits of resolution with no significant degradation in classification accuracy. For 5 bits of resolution, our proposed accelerator yields 5 ×\times× to 63 ×\times× better performance than CMOS and 15 ×\times× to 173 ×\times× better area efficiency than B-SFQ.
In superconducting circuits, information is carried by ps-wide, µV-tall, Single Flux Quanta (SFQ) pulses. These circuits can operate at frequencies of hundreds of GHz with orders of magnitude lower switching energy than complementary-metal-oxide-semiconductors (CMOS). However, under the stringent area constraints of modern superconductor technologies, fully-fledged, CMOS-inspired superconducting architectures cannot be fabricated at large scales. Unary SFQ (U-SFQ) is an alternative computing paradigm that addresses these area constraints. In U-SFQ, information is mapped to a combination of streams of SFQ pulses and in the temporal domain. In this work, we propose a U-SFQ Convolutional Neural Network (CNN) hardware accelerator capable of comparable peak performance with state-of-the-art superconducting binary (B-SFQ) approaches in 32× less area. CNNs can operate with 5 to 8 bits of resolution with no significant degradation in classification accuracy. The proposed CNN accelerator effortlessly supports this variable resolution and, for less than 7 bits, yields 5×-63× better performance than CMOS and 15×-173× better area efficiency than B-SFQ.
In this paper we present an FFT hardware accelerator based on a butterfly (BUT) structure implemented in Rapid Single-Flux-Quantum (RSFQ) superconducting computing. Our design uses a data representation that combines Race Logic (RL) with pulse streams in order to perform arithmetic operations and generate twiddle factors efficiently. Given today’s stringent area limitations for RSFQ technology, our design aims to maximize area efficiency. Our design shows 2 to 18× higher throughput per area, measured as performance per number of Josephson junctions. Moreover, we demonstrate 20-70% area savings compared to binary RSFQ FFT implementations for 2 to 64 N-points.
Abstract With the increasing processor performance requirements of convolutional neural networks, we believe that research on superconducting neural networks based on single flux quantum (SFQ) circuits holds significant potential. However, the typical multiply and accumulate operations used in neural networks often lead to a significant increase in circuit area due to the limitations of the integration density of the current SFQ circuit fabrication process. In this work, we propose a binary neural processing element (PE) that utilizes time-domain signal expression. Time-domain signals express multi-bit binary data in time information, which reduces the number of data lines to decrease the circuit area. In the proposed binary neural PE, multiplication is achieved through exclusive-NOR gates and addition is realized by controlling the delay of time-domain signals. We designed and simulated a 3 × 3 convolution circuit using 10 Nb layer process with a critical current density of 10 kA cm−2. Compared to the convolution circuit implemented using conventional SFQ logic, the proposed circuit reduces the number of Josephson junctions by approximately 56% and decreases the area by about 60%.
Abstract Single-flux-quantum (SFQ) circuits are promising candidates for post-Moore integrated circuits owing to their ultra-high-speed operation and low power consumption. However, limitations in current superconducting fabrication processes pose significant challenges to achieving area-efficient SFQ-based microprocessors, particularly in the design of compact arithmetic logic units (ALUs). Unary computing enables arithmetic operations using extremely simple logic, but typically suffers from long computation latency. This paper focuses on unary computing for superconducting circuits that exploits the complementary characteristics of SFQ logic and unary computing. The ultra-high-speed nature of SFQ circuits compensates for the inherent latency of unary computation, while unary computing enables an ultra-low hardware cost by substantially reducing circuit complexity. Based on this concept, we introduce a unary computing methodology tailored for SFQ circuits and design a superconducting unary ALU with ultra-low hardware cost. The proposed ALU requires only 183 Josephson junctions (JJs), achieving approximately 88.2% reduction in JJ count and 80.4% reduction in area compared with a conventional bit-serial SFQ ALU. The proposed design, including binary-to-unary and unary-to-binary converters, was fabricated using a 10 kA cm −2 Nb four-layer superconducting circuit fabrication process and experimentally verified to operate correctly at approximately 72 GHz. The total power consumption at this frequency is approximately 58.9 µ W. This work quantitatively demonstrates the effectiveness of combining unary computing with SFQ circuits for ultra-low-cost processing systems and provides superconducting circuits as a new design option for alternative computation paradigms, such as unary computing.
Temporal encoding has been shown to be a natural fit for single flux quantum (SFQ) superconducting computing since SFQ already encodes information with the presence or absence of voltage pulses. However, past work in SFQ has focused on binary-encoded networks on chip (NoCs). In this paper, we propose superconducting rotary NoC (SRNoC), a NoC where both data and control paths operate in the temporal domain following the race logic (RL) convention. Therefore, SFQ chips with temporal compute or memory can use SRNoC to avoid converting between the temporal and binary domains that would result from using a binary-encoded NoC. Using RL also enables SRNoC to be area-efficient, mitigating SFQ technology's low device density. SRNoC treats pulses as independent packets and delivers them to outputs without changing their value, i.e. preserving the RL convention. SRNoC operates on a fixed, rotating connection schedule between inputs and outputs. In each connection window, multiple pulses (packets) can be transmitted sequentially. SRNoC provides 13.1x higher throughput per port per Josephson junction (JJ) compared to the best-performing of three demonstrated NoCs.