Algorithms, gates and error correction for the Kane quantum computer

This thesis deals with a series of quantum computer implementation issues from the Kane 31P in 28Si architecture to Shor's integer factoring algorithm and beyond. The discussion begins with simulations of the adiabatic Kane CNOT and readout gates, followed by linear nearest neighbor implementations of 5-qubit quantum error correction with and without fast measurement. A linear nearest neighbor circuit implementing Shor's algorithm is presented, then modified to remove the need for exponentially small rotation gates. Finally, a method of constructing optimal approximations of arbitrary single-qubit fault-tolerant gates is described and applied to the specific case of the remaining rotation gates required by Shor's algorithm.This thesis deals with a series of quantum computer implementation issues from the Kane 31P in 28Si architecture to Shor's integer factoring algorithm and beyond. The discussion begins with simulations of the adiabatic Kane CNOT and readout gates, followed by linear nearest neighbor implementations of 5-qubit quantum error correction with and without fast measurement. A linear nearest neighbor circuit implementing Shor's algorithm is presented, then modified to remove the need for exponentially small rotation gates. Finally, a method of constructing optimal approximations of arbitrary single-qubit fault-tolerant gates is described and applied to the specific case of the remaining rotation gates required by Shor's algorithm.

arXiv:quant-ph/0506126Jun 16, 200515 citations

Error Correction for Quantum Computers

WORLD SCIENTIFIC eBooksJul 1, 19980 citations

Gates for the Kane quantum computer in the presence of dephasing

Charles D. Hill, Hsi‐Sheng Goan

In this paper we investigate the effect of dephasing on proposed quantum gates for the solid-state Kane quantum computing architecture. Using a simple model of the decoherence, we find that the typical error in a controlled-NOT gate is $8.3\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}5}$. We also compute the fidelities of $Z$ , $X$ , swap, and controlled $Z$ operations under a variety of dephasing rates. We show that these numerical results are comparable with the error threshold required for fault tolerant quantum computation.In this paper we investigate the effect of dephasing on proposed quantum gates for the solid-state Kane quantum computing architecture. Using a simple model of the decoherence, we find that the typical error in a controlled-NOT gate is $8.3\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}5}$. We also compute the fidelities of $Z$, $X$, swap, and controlled $Z$ operations under a variety of dephasing rates. We show that these numerical results are comparable with the error threshold required for fault tolerant quantum computation.

arXiv:quant-ph/0405042Physical Review AAug 1, 200414 citations

Quantum Error Correction with Imperfect Gates

Alexei Kitaev

Springer eBooksJan 1, 1997212 citations

Error Correction in Quantum Computing

Jesús Yaljá Montiel-Pérez, Jordi Fabián González-Contreras, Erik Zamora +1 more

Studies in computational intelligenceJan 1, 20250 citations

Silicon quantum computation based on magnetic dipolar coupling

Rogério de Sousa, J. D. Delgado, S. Das Sarma

A dipolar gate alternative to the exchange-gate-based Kane quantum computer is proposed where the qubits are electron spins of shallow group V donors in silicon. Residual exchange coupling is treated as gate error amenable to quantum error correction, removing the stringent requirements on donor positioning characteristic of all silicon exchange-based implementations [Koiller et al., Phys. Rev. Lett. 88, 027903 (2002)]. Contrary to common speculation, such a scheme is scalable with no overhead in gating time even though it is based on long-range dipolar interqubit coupling.A dipolar gate alternative to the exchange-gate-based Kane quantum computer is proposed where the qubits are electron spins of shallow group V donors in silicon. Residual exchange coupling is treated as gate error amenable to quantum error correction, removing the stringent requirements on donor positioning characteristic of all silicon exchange-based implementations [Koiller et al., Phys. Rev. Lett. 88, 027903 (2002)]. Contrary to common speculation, such a scheme is scalable with no overhead in gating time even though it is based on long-range dipolar interqubit coupling.

arXiv:cond-mat/0311403Physical Review ANov 5, 200497 citations

Z

X

, swap, and controlled

Z

operations under a variety of dephasing rates. We show that these numerical results are comparable with the error threshold required for fault tolerant quantum computation.