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Journal of Science and Technology on Information security

Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder

Huyen Thi Pham, Hung Tuan Dao, Nghia Xuan Pham

Published Apr 9, 2020• 0 citations
Publisher

Abstract

Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.Tóm tắt— Các mã LDPC phi nhị phân (NB-LDPC) vượt trội so với các mã LDPC nhị phân về chất lượng sửa lỗi và thuộc tính lỗi san bằng khi chiều dài là trung bình. Tuy nhiên, nhược điểm của các bộ giải mã NB-LDPC là tính phức tạp cao và độ phức tạp tăng đáng kể khi bậc của trường Galois cao. Trong bài báo này, thuật toán Trellis Min-Max dựa trên tập cơ sở được đơn giản hóa được đề xuất cho xử lý nốt biến mà hiệu quả cho các trường Galois bậc cao để giảm độ phức tạp của khối nốt biến (VNU) cũng như cả bộ giải mã. Kiến trúc bộ giải mã tương ứng với thuật toán đề xuất được thiết kế cho mã NB-LDPC (837, 726) thông qua trường GF(32). Các kết quả thực hiện sử dụng công nghệ CMOS 90-nm chỉ ra rằng kiến trúc bộ giải mã được đề xuất giảm số lượng cổng logic 21,35% và 9,4% với chất lượng sửa lỗi gần như không thay đổi so với các nghiên cứu gần đây.

DOI
10.54654/isj.v9i01.36

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Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.Tóm tắt— Các mã LDPC phi nhị phân (NB-LDPC) vượt trội so với các mã LDPC nhị phân về chất lượng sửa lỗi và thuộc tính lỗi san bằng khi chiều dài là trung bình. Tuy nhiên, nhược điểm của các bộ giải mã NB-LDPC là tính phức tạp cao và độ phức tạp tăng đáng kể khi bậc của trường Galois cao. Trong bài báo này, thuật toán Trellis Min-Max dựa trên tập cơ sở được đơn giản hóa được đề xuất cho xử lý nốt biến mà hiệu quả cho các trường Galois bậc cao để giảm độ phức tạp của khối nốt biến (VNU) cũng như cả bộ giải mã. Kiến trúc bộ giải mã tương ứng với thuật toán đề xuất được thiết kế cho mã NB-LDPC (837, 726) thông qua trường GF(32). Các kết quả thực hiện sử dụng công nghệ CMOS 90-nm chỉ ra rằng kiến trúc bộ giải mã được đề xuất giảm số lượng cổng logic 21,35% và 9,4% với chất lượng sửa lỗi gần như không thay đổi so với các nghiên cứu gần đây.
Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.
Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.
Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance when the code length is moderate. Check node processing is a bottleneck of the NB-LDPC decoding. In this paper, a novel half-row modified two-extra-column trellis min-max (HR-mTEC-TMM) algorithm is proposed for the check node processing to reduce not only the complexity but also the storage memory. The check node unit (CNU) architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed CNU architecture obtains a reduction of 28.3% for the area and 43.87% for the storage memory with an acceptable error-correcting performance loss, compared to existing work.
Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.
Limitations on hardware resource consumption and throughput make the use of non-binary low-density parity-check (NB-LDPC) codes challenging in practical applications. This brief first proposes a novel check-node (CN) decoding algorithm called Hamming-distance trellis min-max (H-TMM) to reduce the complexity introduced by searching for two minimum values in previous TMM-based algorithms. Then, by taking advantage of the proposed algorithm and the number appearances of reliable values, a high-performance H-TMM-based NB-LDPC decoder architecture is presented. Experiments on the 32-ary (837, 726) NB-LDPC code confirmed that the proposed decoder can obtain a high throughput on less hardware resources compared with the state-of-the-art works while maintaining a competitive error-correcting performance. In particular, the proposed CN unit architecture reduced hardware resources by almost half compared to that in the latest decoder.
Low-density parity-check (LDPC) codes defined over non-binary (NB) finite field GF(2q)(q >1) achieve better error-correcting performance than binary LDPC codes when the codeword length is moderate. The decoder complexity increases very fast with the order of the field, 2q, although the error-correcting performance also improves. To reduce the complexity for practical applications, NB-LDPC codes over lower-order finite fields are of great interest. Previous designs have been focusing on decoders over either the smallest NB field GF (4) or much larger fields, such as GF (32) or higher. Prior optimization techniques are either not applicable or do not lead to efficient designs for codes over GF (8) or other lower-order fields. In this paper, an efficient architecture is developed for the check node processing, which is the most complicated step in NB-LDPC decoding, for the Min-max algorithm over lower-order fields. By utilizing the properties of finite field elements, the max/min comparison results are shared and the number of comparators needed is reduced significantly. Compared to the best prior design, the proposed check node processing has 18.5% smaller area and shorter critical path for an example code over GF (8).