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Message Passing Algorithm and Linear Programming Decoding for LDPC and Linear Block Codes

Tobias Lindstrøm Jensen, Nano Thaore, Shashi Kant

Published Jan 1, 2007• 5 citations
OpenAlex

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Low-density parity-check (LDPC) codes are one of the most popular linear block codes have ever been used in the communication system.The standard two-phase message passing decoding (TPMPD) algorithm and the layered message-passing decoding (LMPD) algorithm are widely used in LDPC decoder.However, the convergence speed of LMPD algorithm is much faster than that of TPMPD algorithm, particularly in the condition of high signal noise ratio (SNR).In this paper, we propose an early termination criterion for quasi-cyclic low-density parity-check (QC-LDPC) codes based on LMPD algorithm with fast convergence speed.The strategy is to dynamically reprocesses the uncorrected related layers while skipping the corrected ones.Simulations show that 3% reduction in terms of iteration numbers can be achieved with no performance loss compared to the traditional termination strategies, such as hard decision aided (HDA) strategy and parity check equations (PCE) strategy.Furthermore, the optimized early termination strategy achieves low complexity in hardware implementation.

Advances in intelligent systems research/Advances in Intelligent Systems Research•Jan 1, 2013•1 citation
Low density parity check (LDPC) codes are one of the most popular channel codes.Based on traditional sum-product and max-product algorithms, various modified algorithms are tried to improve the performance of LDPC codes in terms of error rate, complexity and latency.Uniformly rweighted belief propagation (URW-BP) algorithm can offer better performance than traditional algorithm especially for regular LDPC codes.linear programming (LP) decoder is also competitive to traditional message passing algorithm.We describe two traditional message passing decoders, four reweighted message passing decoders based on URW-BP and LP decoder in this paper.Reweighted decoders can outperform traditional decoders especially when iteration number is limited.Considering complexity and latency, reweighted max product decoder of version 2 (R-MPD-II) is the most promising decoder.CONTENTS 4.3 Short regular LDPC codes . . . . . . . .
Linear programming (LP) decoding is an alternative to iterative algorithms for decoding low density parity check (LDPC) codes. Although the practical performance of LP decoding is comparable to message-passing decoding, a significant advantage is its relative amenability to nonasymptotic analysis. Moreover, there turn out to be a number of important theoretical connections between the LP decoding and standard forms of iterative decoding. These connections allow theoretical insight from the LP decoding perspective to be transferred to iterative decoding algorithms. These advantages encouraged many researchers to work in this recent decoding technique for LDPC codes. In this paper, LP decoding for LDPC code is extensively reviewed and is discussed in different segmented areas.
Low-density parity-check (LDPC) codes are one of the most popular linear block codes have ever been used in the communication system.The standard two-phase message passing decoding (TPMPD) algorithm and the layered message-passing decoding (LMPD) algorithm are widely used in LDPC decoder.However, the convergence speed of LMPD algorithm is much faster than that of TPMPD algorithm, particularly in the condition of high signal noise ratio (SNR).In this paper, we propose an early termination criterion for quasi-cyclic low-density parity-check (QC-LDPC) codes based on LMPD algorithm with fast convergence speed.The strategy is to dynamically reprocesses the uncorrected related layers while skipping the corrected ones.Simulations show that 3% reduction in terms of iteration numbers can be achieved with no performance loss compared to the traditional termination strategies, such as hard decision aided (HDA) strategy and parity check equations (PCE) strategy.Furthermore, the optimized early termination strategy achieves low complexity in hardware implementation.