This chapter discusses the overall hardware architecture of a quantum processor. Emulation of quantum processing requires primarily an efficient way to store and retrieve quantum information. The quantum processor employs different purpose memories. The proposed co-processor implements a quantum machine capable of performing certain quantum operations on a set of q-bits that form the machine quantum state. It is an isolated system that interacts with a host processor through communication channels. The main processor sends properly formatted commands that invoke quantum operations on q-bits, to manipulate the quantum state. The channel configuration is used because it considers the sequential characteristic of a quantum algorithm due to the potential dependence of the result of the previous operation on one or more q-bits. The full-duplex configuration would also be possible, given the required control related to data dependency. The interaction between the units and memories that compose the co-processor is done via data buses, address buses and/or control buses.
High qubit overhead is a key bottleneck for fault-tolerant quantum computation. Quantum low-density parity-check (qLDPC) codes offer high encoding efficiency but typically require non-local connectivity in every syndrome extraction cycle, incurring additional physical errors and implementation complexity. We introduce a hierarchical logical processor (HLP) architecture that implements a high-rate quantum CSS code with distance-d0 rotated surface codes (RSC), allowing long-range connectivity to be used only once every Θ(d0) rounds of surface-code syndrome extraction. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of 10−3, a hierarchical logical processor can achieve 3-4 times higher qubit efficiency than the rotated surface code and 20-30 times shorter logical error-correction cycle times than the yoked surface code.
Microwave photons are used to wire up modular quantum processors, but mitigating the effects of loss between modules remains a crucial challenge.We use a low-loss bus resonator to couple bosonic qubits across a superconducting network with protocols made robust to photon loss in the bus.We transfer a multiphoton qubit and track loss events, improving the fidelity to the break-even point with respect to the best uncorrectable encoding.We also demonstrate a entanglement protocol using Hong-Ou-Mandel interference and error detection to prepare a two-photon Bell state with fidelity 94% and success probability 0.79, halving the error obtained with a single photon.This network link also presents new opportunities for resource-efficient direct gates between modules.