Scalable Quantum Circuit Optimization Using Automated Synthesis

Timothée Goubault de Brugière, Marc Baboulin, Benoît Valiron +1 more

Xin-Chuan Wu, Davis, Marc Grau, Frederic T. Chong +1 more

The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.

Colin P. Williams, Alexander Gray

Mathias Soeken, Anupam Chattopadhyay

Latest quantum technologies promise realization of extremely large circuits, whereas, reversible logic synthesis, the key automation step for quantum computing, suffers from scalability bottleneck. Scalability can be achieved with Decision Diagram (DD)-based synthesis at the cost of significant an-cilla/garbage lines overhead. In this paper, we present a novel hierarchical reversible logic synthesis, where DD-based synthesis is invoked within an And-Inverter Graph (AIG)-based synthesis wrapper, balancing scalability and performance.

Radja Mermoul, Ayyoub Slimani, Achour Benslama

Abstract Efficient quantum comparators are a key building block in quantum algorithms, but their practical utilization during the Noisy Intermediate-Scale Quantum (NISQ) era is limited by high resource demands. In this paper, we present an automated and scalable approach focused on the synthesis of optimal n-bit quantum comparator circuits that significantly minimize key quantum parameters, namely quantum cost (QC), quantum delay (QD), and garbage outputs (GO). Our approach uses a dynamic algorithmic framework built with Python and Qiskit to adapt the circuit design based on the size of the input operands. This enables the automatic generation of resource-efficient, modular designs. Through systematic optimization of qubit assignment, gate ordering, and sub-circuit composition, our full circuit achieves substantial performance gains. Experimental validation using 4-bit comparators demonstrates 14.89% reduction in QC, 12.5% in QD, and 18.75% in GO over state-of-art designs, as validated through noise-free simulations under NISQ-era limitations. Although the algorithmic scalability of the produced circuits allows straightforward generalization to any n-bit operands without any loss in optimization quality. These findings confirm the effectiveness of our approach, suggesting that it may lead to further optimizations for related quantum circuits, including as Arithmetic Logic Units.

Mariam Zomorodi Moghadam, Mohammad Amin Taherkhani, Keivan Navi