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physica status solidi (b)

Large‐Scale Fabrication of Surface Ion Traps on a 300 mm Glass Wafer

Jing Tao, J.-P. Likforman, Peng Zhao, Hong Yu Li, Théo Henner, Yu Dian Lim, Wen Wei Seit, Luca Guidoni, Chuan Seng Tan

Published May 1, 2021• 4 citations
Publisher

Abstract

Herein, a large‐scale fabrication of radio frequency (RF) surface ion traps on a 300 mm glass wafer using a standard foundry process is reported. Established wafer‐level packaging process of electroplated Cu with Au finish is used to fabricate the surface electrodes directly on the glass wafer substrate. A trap is tested by loading it with laser‐cooled 88Sr+ ions. The trap shows a stable operation with RF amplitudes in the range of 100–250 V at 33 MHz frequency. The ion lifetime is on the order of 30 min with laser cooling with a vacuum chamber pressure of ≈5 × 10−11 mbar. These results demonstrate the potential of large‐size foundry glass substrates to realize scalable and integratable trapped ion‐based quantum devices.

DOI
10.1002/pssb.202000589

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Herein, a large‐scale fabrication of radio frequency (RF) surface ion traps on a 300 mm glass wafer using a standard foundry process is reported. Established wafer‐level packaging process of electroplated Cu with Au finish is used to fabricate the surface electrodes directly on the glass wafer substrate. A trap is tested by loading it with laser‐cooled 88Sr+ ions. The trap shows a stable operation with RF amplitudes in the range of 100–250 V at 33 MHz frequency. The ion lifetime is on the order of 30 min with laser cooling with a vacuum chamber pressure of ≈5 × 10−11 mbar. These results demonstrate the potential of large‐size foundry glass substrates to realize scalable and integratable trapped ion‐based quantum devices.
We report large-scale fabrication of perfectly functional radio frequency (RF) surface ion traps on a 12-inch glass substrate with a standard CMOS-compatible backend process. Established 12-inch foundry backend process of electroplated Cu with Au finish are employed to fabricate the surface electrodes directly on the glass wafer substrate. We tested a trap by loading it with laser-cooled 88 Sr + ions. The trap shows a stable operation with RF amplitude in the range 100-230 V at 33 MHz frequency. The ion lifetime is on the order of 30 minutes for a pressure in the vacuum chamber of 5 x 10-11 mbar, which demonstrates an exciting potential for future implementation of quantum computing system with a standard foundry process on CMOS compatible and cost-effective platform.
This article presents the design and development of surface electrode ion traps on glass and Si substrates and their radio frequency (RF) characterizations and performance benchmarking. In this case, the ion trap on glass shows superior performances in all necessary criteria. In terms of RF characterizations, ion traps on glass have aQ{Q}Qfactor of greater than 900. This is significantly higher than theQ{Q}Qfactor of its silicon counterparts, which are around 20–300. Such a highQ{Q}Qfactor results in power spectral density (PSD) of greater than 10 W/MHz. On the other hand, ion traps on silicon produce PSD values of lower than 3 W/MHz. In terms of RF performance, the ion trap on glass shows insertion loss lower than 0.2 dB at 60 MHz. This is more superior to insertion loss values of ion traps on silicon, which are around 1–4 dB. The ion-traps metallization is developed using three metallization layers (0.1-μm\mu \text{m}μmTi barrier layer, 2.5–3.7-μm\mu \text{m}μmCu, and 0.3-μm\mu \text{m}μmAu) on top of the dielectric. The on-chip resonance condition can be maintained upon packaging integration. The laser optical setup for ion trapping is verified to capture a single88Sr+ion.
In this study, we report about the design, fabrication, and operation of a Cu-filled through-silicon via (TSV)-integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between an ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrode numbers and evolving complexity. The integration of TSVs reduces the form factor of the ion trap by more than 80%, minimizing parasitic capacitance from 32 ± 2 to 3 ± 0.2 pF. A low RF dissipation is achieved in spite of the absence of the ground screening layer. The entire fabrication process is on a 12-in. wafer and compatible with the established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (∼30 min) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
Si substrates provide flexible platform for quantum application that can integrate photonic components, active devices, and metal electrodes. Photonics integrated surface ion trap can effectively integrate the functionality of photonics integrated circuits and ion traps on the same Si-substrate. The ion trap electrodes are fabricated on a 300mm high resistivity substrate. Both leakage current and capacitance meet the device factional requirements at the wafer scale. The loaded Q-factor of the package at 9.8K is over 20, allowing application of 300V RF at low power at a trap drive frequency of 16 MHz for barium ion.
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.