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Quantum Science and Technology

Optimal calibration of gates in trapped-ion quantum computers

Andrii Maksymov, Pradeep Niroula, Yunseong Nam

Published Apr 12, 2021• 9 citations
Publisher

Abstract

Abstract To harness the power of quantum computing, it is essential that a quantum computer provide maximal possible fidelity for a quantum circuit. To this end, much work has been done in the context of qubit routing or embedding, i.e., mapping circuit qubits to physical qubits based on gate performance metrics to optimize the fidelity of execution. Here, we take an alternative approach that leverages a unique capability of a trapped-ion quantum computer, i.e., the all-to-all qubit connectivity. We develop a method to determine a fixed number (budget) of quantum gates that, when calibrated, will maximize the fidelity of a batch of input quantum programs. This dynamic allocation of calibration resources on randomly accessible gates, determined using our heuristics, increases, for a wide range of calibration budget, the average fidelity from 70% or lower to 90% or higher for a typical batch of jobs on an 11-qubit device, in which the fidelity of calibrated and uncalibrated gates are taken to be 99% and 90%, respectively. Our heuristics are scalable, more than 2.5 orders of magnitude faster than a randomized method for synthetic benchmark circuits generated based on real-world use cases.

DOI
10.1088/2058-9565/abf718

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Abstract To harness the power of quantum computing, it is essential that a quantum computer provide maximal possible fidelity for a quantum circuit. To this end, much work has been done in the context of qubit routing or embedding, i.e., mapping circuit qubits to physical qubits based on gate performance metrics to optimize the fidelity of execution. Here, we take an alternative approach that leverages a unique capability of a trapped-ion quantum computer, i.e., the all-to-all qubit connectivity. We develop a method to determine a fixed number (budget) of quantum gates that, when calibrated, will maximize the fidelity of a batch of input quantum programs. This dynamic allocation of calibration resources on randomly accessible gates, determined using our heuristics, increases, for a wide range of calibration budget, the average fidelity from 70% or lower to 90% or higher for a typical batch of jobs on an 11-qubit device, in which the fidelity of calibrated and uncalibrated gates are taken to be 99% and 90%, respectively. Our heuristics are scalable, more than 2.5 orders of magnitude faster than a randomized method for synthetic benchmark circuits generated based on real-world use cases.
Trapped-ion (TI) quantum computer is one of the forerunner quantum technologies. Execution of a quantum gate in multiple trap TI system may frequently involve ions from two different traps, hence one of the ions needs to be shuttled (moved) between traps to be co-located, degrading fidelity, and increasing the program execution time. The choice of initial mapping influences the number of shuttles. The existing Greedy policy neglects the depth of the program at which a gate is present. Intuitively, the contribution of the late-stage gates to the initial mapping is less since the ions might have already shuttled to a different trap to satisfy other gate operations. In this paper, we target this gap and propose a new program adaptive policy especially for programs with considerable depth and high number of qubits (valid for practical-scale quantum programs). Our technique achieves an average reduction of 9% shuttles/program (with 21.3% at best) for 120 random circuits and enhances the program fidelity up to 3.3X (1.41X on average).
Near-term quantum computations are limited by high error rates, the scarcity of qubits and low qubit connectivity. Increasing support for mid-circuit measurements and qubit reset in near-term quantum computers enables qubit reuse that may yield quantum computations with fewer qubits and lower errors. In this work, we introduce a formal model for qubit reuse optimization that delivers provably optimal solutions with respect to quantum circuit depth, number of qubits, or number of swap gates for the first time. This is in contrast to related work where qubit reuse is used heuristically or optimally but without consideration of the mapping effort. We further investigate reset errors on near-term quantum computers by performing reset error characterization experiments. Using the hereby obtained reset error characterization and calibration data of a near-term quantum computer, we then determine a qubit assignment that is optimal with respect to a given cost function. We define this cost function to include gate errors and decoherence as well as the individual reset error of each qubit. We found the reset fidelity to be state-dependent and to range, depending on the reset qubit, from 67.5% to 100% in a near-term quantum computer. We demonstrate the applicability of the developed method to a number of quantum circuits and show improvements in the number of qubits and swap gate insertions, estimated success probability, and Hellinger fidelity of the investigated quantum circuits.
Quantum computers with a limited qubit connectivity require inserting SWAP gates for qubit routing, which increases gate execution errors and the impact of environmental noise due to an overhead in circuit depth. In this work, we benchmark various routing techniques considering random quantum circuits on one-dimensional and square lattice connectivities, employing both analytical and numerical methods. We introduce circuit fidelity as a comprehensive metric that captures the effects of SWAP and circuit depth overheads. Leveraging a novel approach based on the SABRE algorithm, we achieve up to 84%84\%84% higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.
Abstract The field of quantum computing has grown from concept to demonstration devices over the past 20 years. Universal quantum computing offers efficiency in approaching problems of scientific and commercial interest, such as factoring large numbers, searching databases, simulating intractable models from quantum physics, and optimizing complex cost functions. Here, we present an 11-qubit fully-connected, programmable quantum computer in a trapped ion system composed of 13 171 Yb + ions. We demonstrate average single-qubit gate fidelities of 99.5 %\%% % , average two-qubit-gate fidelities of 97.5 %\%% % , and SPAM errors of 0.7 %\%% % . To illustrate the capabilities of this universal platform and provide a basis for comparison with similarly-sized devices, we compile the Bernstein-Vazirani and Hidden Shift algorithms into our native gates and execute them on the hardware with average success rates of 78 %\%% % and 35 %\%% % , respectively. These algorithms serve as excellent benchmarks for any type of quantum hardware, and show that our system outperforms all other currently available hardware.
We present an analysis of quantum circuit fidelity across the full compilation stack, from high-level gate optimization through pulse-level control. We connect a C++ circuit optimizer to a per-gate Lindblad master-equation fidelity model whose decoherence channels are cross-validated against qiskit-dynamics and whose absolute predictions are benchmarked against execution on real hardware. Across a campaign of 4,452 experiment runs over 371 benchmark circuits, gate cancellation provides the dominant improvement (d=1.66d = 1.66d=1.66, 72% of circuits improved), while circuit size and pulse duration are the strongest negative predictors of process fidelity (input gates r=−0.78r = -0.78r=−0.78; pulse duration r=−0.73r = -0.73r=−0.73, R2=0.53R^2 = 0.53R2=0.53). A formal ablation study shows that pass ordering has no significant effect on two-qubit gate reduction (Kruskal--Wallis p=0.302p = 0.302p=0.302). Comparing against Qiskit transpilation levels, we show that two-qubit gate count, not total gate count, is the hardware-relevant metric: our optimizer attains superior two-qubit reduction on structured circuits (87.8% on QFT, 100% on QAOA) whereas Qiskit's larger total-gate reduction is dominated by single-qubit (u3u_3u3​) consolidation. Finally, executing eight circuits on the IQM Resonance Garnet processor (8/8 jobs completed, job identifiers released) reveals that the model is a consistent upper bound: it preserves the relative difficulty ordering of circuits but overestimates absolute fidelity by a mean of 0.49, quantifying the error budget (crosstalk, leakage, readout) outside a T1T_1T1​/T2T_2T2​/depolarizing model. We release the framework, data, and scripts as open source.
Trapped-ion quantum computers offer high-fidelity operations, long coherence times, and all-to-all connectivity within a single trap. However, scaling to large circuits is limited by the trap's ion capacity. The QCCD architecture addresses this by enabling ion shuttling across multiple traps, but excessive shuttling increases execution time and degrades fidelity. This paper presents an improved ion-shuttling approach targeting linear QCCD architectures. Building on a state-of-the-art approach [27] for linear trapped-ion devices, our approach introduces a front-layer-based scheduling method that dynamically prioritizes executable gates, along with a novel destination trap selection method for ion-shuttling, effectively reducing unnecessary ion movements. We also present a look-ahead gate selection strategy based on the gate dependency graph, avoiding the high runtime of the gate proximity approach used in the state-of-the-art approach, especially in circuits with all-to-all communication. Our approach achieves up to a 37.67% reduction in shuttle count and up to a 74.91% reduction in compilation time compared to the state-of-the-art approach for linear trapped-ion devices on actual NISQ benchmarks and synthetic circuits. On average, our approach achieves a 16.44% reduction in shuttle count and a 30.77% reduction in compilation time across all test cases. These improvements highlight the effectiveness of our approach, particularly for actual circuits.