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Frontiers of Electrical and Electronic Engineering in China

Iterative hybrid decoding algorithm for LDPC codes based on attenuation factor

Minghua, Liu, Lijun, Zhang

Published Jan 1, 2012• 0 citations
OpenAlex

Abstract

为低密度的同等值检查(LDPC ) 译码算法编码的稀释反复的基于可靠性的多数逻辑(AIML ) 被建议，它与译码计划的混血儿相关。算法基于译码算法与一起的一步舞 majoritylogic (OSMLG ) 的直角的校验和被设计收到的符号的可靠性措施肯定。症候群和的可靠性措施的计算被介绍一个变细因素精制。模拟结果显示出那，在二进制输入的添加剂白人 Gaussian 噪音(BI-AWGN ) 隧道，译码算法的 AIML 超过随计算复杂性的细微增加译码算法的另外的流行反复的基于可靠性的多数逻辑(IML ) 。在 5 的最大的重复数字以内， AIML 算法能完成几乎相同的错误性能到和产品算法(矿泉) 。没有错误地板效果能为 AIML 算法被观察击倒到 108 的小点错误率(BER ) ，当错误地板在 BER 附近为矿泉出现时 107 甚至与 100 的最大的重复数字。而且，为 AIML 算法的平行行列的固有的特征与那些连续译码计划相对照强制译码的速度，例如加权扭动小点(WBF ) 算法。

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Iterative hybrid decoding algorithm for LDPC codes based on attenuation factor

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为低密度的同等值检查(LDPC ) 译码算法编码的稀释反复的基于可靠性的多数逻辑(AIML ) 被建议，它与译码计划的混血儿相关。算法基于译码算法与一起的一步舞 majoritylogic (OSMLG ) 的直角的校验和被设计收到的符号的可靠性措施肯定。症候群和的可靠性措施的计算被介绍一个变细因素精制。模拟结果显示出那，在二进制输入的添加剂白人 Gaussian 噪音(BI-AWGN ) 隧道，译码算法的 AIML 超过随计算复杂性的细微增加译码算法的另外的流行反复的基于可靠性的多数逻辑(IML ) 。在 5 的最大的重复数字以内， AIML 算法能完成几乎相同的错误性能到和产品算法(矿泉) 。没有错误地板效果能为 AIML 算法被观察击倒到 108 的小点错误率(BER ) ，当错误地板在 BER 附近为矿泉出现时 107 甚至与 100 的最大的重复数字。而且，为 AIML 算法的平行行列的固有的特征与那些连续译码计划相对照强制译码的速度，例如加权扭动小点(WBF ) 算法。
为实际考虑，加速在一个反复的译码系统使用的译码的算法的集中速度是必要的。在这份报纸，为低密度的同等值检查(LDPC ) 译码算法编码的水平洗牌的复制品版本被建议改进原来的版本的集中速度。外来的信息转移(出口) 图表技术被扩大到建议算法预言他们的集中行为。退出图表分析，数字结果证明译码的复制品平原水平洗牌(RPHS ) 比译码的平凡水平洗牌(PHS ) 和译码的标准信仰繁殖(BP ) 快集成大部分。而且，译码的复制品组水平洗牌(RGHS ) 能增加译码的 RPHS 的并行以及如果一个等价条件满足，保存它的高集中速度，这也被揭示，并且对硬件实现因此合适。
代码基于有限的地被建议的伪周期的低密度的同等值检查(QC-LDPC ) 的一个新奇构造方法趋于增加的组，举办更容易的建设，更灵活的代码长度代码率调整和更低的编码 / 译码复杂性。而且，常规 QC-LDPC (5334,4962 ) 代码被构造。模拟结果证明构造 QC-LDPC (5334,4962 ) 代码能在添加剂白人 Gaussian 噪音(AWGN ) 的条件下面获得更好的错误修正性能有反复的译码的隧道和产品算法(矿泉) 。以 106 的小点错误率( BER )，编码构造 QC-LDPC ( 5334,4962 )代码的获得( NCG )的网是多于在 ITU-T G.975 的经典 RS ( 255,239 )代码的 1.8 dB ， 0.9 dB 和 0.2 dB ，在代码分别地由随机的方法构造了的 ITU-T G.975.1 和 SCG-LDPC ( 3969,3720 )的 LDPC ( 32640,30592 )代码。它因此对光通讯系统更合适。
Low-density parity-check (LDPC) 부호의 복호에는 성능이 좋은 합곱 알고리즘(sum-product algorithm; SPA)과 하드웨어가 간단한 비트 반전(bit-flipping; BF) 알고리즘이 많이 쓰이고 있다. 본 논문은 이들 두 가지 방법의 장점을 가지는 저복잡도 고성능 복호 알고리즘을 제안한다. 본 제안된 유연 비트 반전(soft bit-flipping) 알고리즘은 비트와 체크 노드 사이에 전달되는 메시지를 계산하는 데 단순한 비교와 덧셈 연산만을 필요로 하며 연산량이 적다는 장점이 있다. 또한 연산이 완료된 메시지의 활용률을 높이고 비균등 양자화(non-uniform quantization)를 채용하여 1000 내외의 부호 길이에서 SPA 에 0.4dB 근접하는 신호대 잡음비(signal-to-noise ratio)를 달성하였다. 본 논문에서 제안된 알고리즘을 이용하면, 행 무게(row weight)와 열 무게(column weight)가 높아서 종래의 SPA로 구현하기 어려웠던 부호를 비교적 좋은 오율 성능을 유지하면서 실용적으로 구현할 수 있다. ; A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.
An attenuated iterative reliability-based majority-logic (AIML) decoding algorithm for low-density parity-check (LDPC) codes is proposed. This novel algorithm is devised based on the orthogonal check-sums of the one-step majority-logic decoding algorithm in conjunction with certain of reliability measures of the received symbols. The computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that in binary input-additive white Gaussian noise channel, the AIML algorithm outperforms other popular iterative reliability-based majority-logic decoding algorithms with a slight increase in computational complexity. With maximum iterations five and fifty, the AIML algorithm can achieve almost identical error performance for LDPC codes. No error floor effect can be observed for AIML algorithm down to the bit error rate (BER) of 10−8, while error floor appears for sum product algorithm (SPA) around the BER of 10−7even with maximum iteration 100. The inherent feature of parallel decoding for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping algorithm.