The development of large-scale quantum computers will require the implementation of scalable control electronics, which may have to operate at temperatures as low as 4 K. In this paper, we review a first-generation control IC that has been implemented for use with transmon qubits. We first explain the requirements which such an IC must meet and then present the circuit design. We next describe a series of quantum control experiments carried out with the IC. The paper concludes with a discussion of future work.
The development of large-scale quantum computers will require the implementation of scalable control electronics, which may have to operate at temperatures as low as 4 K. In this paper, we review a first-generation control IC that has been implemented for use with transmon qubits. We first explain the requirements which such an IC must meet and then present the circuit design. We next describe a series of quantum control experiments carried out with the IC. The paper concludes with a discussion of future work.
This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems.
Implementation of an error-corrected quantum computer is believed to require a quantum processor with a million or more physical qubits, and, in order to run such a processor, a quantum control system of similar scale will be required. Such a controller will need to be integrated within the cryogenic system and in close proximity with the quantum processor in order to make such a system practical. Here, we present a prototype cryogenic CMOS quantum controller designed in a 28-nm bulk CMOS process and optimized to implement a 16-word (4-bit)XYgate instruction set for controlling transmon qubits. After introducing the transmon qubit, including a discussion of how it is controlled, design considerations are discussed, with an emphasis on error rates and scalability. The circuit design is then discussed. Cryogenic performance of the underlying technology is presented, and the results of several quantum control experiments carried out using the integrated controller are described. This article ends with a comparison to the state of the art and a discussion of further research to be carried out. It has been shown that the quantum control IC achieves promising performance while dissipating less than 2 mW of total ac and dc power and requiring a digital data stream of less than 500 Mb/s.
Future generations of quantum computers are expected to operate in a paradigm where multi-qubit devices will predominantly perform circuits to support quantum error correction. Highly integrated cryogenic electronics are a key enabling technology to support the control of the large numbers of physical qubits that will be required in this fault-tolerant, error-corrected regime. Here, we describe our perspectives on cryoelectronics-driven qubit control architectures, and will then describe an implementation of a scalable, low-power, cryogenic qubit state controller that includes a domain-specific processor and a SSB upconversion I/Q-mixer-based RF AWG. We will also describe an FPGA-based emulation platform that is able to closely reproduce the system intention, and which was used to verify different aspects of the ASIC system design in in situ transmon qubit control experiments.
The core of a quantum computer is a quantum processor, which is composed of quantum bits (qubits). Qubits can be implemented in many flavors, but they are fragile, and their state has a tendency to decay in time. To be usable for computation, qubits must be corrected in real time by a classical controller. The controller must also see that desired computations are executed. Today, the control of qubits is performed at room temperature (RT) by racks of instruments, while the qubits operate at several tens of milli-Kelvin. To ensure compactness and, eventually, scalability, we have proposed and implemented CMOS circuits designed to operate at a few degrees Kelvin. This makes complex thermalization circuits unnecessary, potentially enabling superconductive interconnects, which would enable virtually zero resistance and low thermal conductivity. Cryogenic CMOS, or cryo-CMOS, technology was chosen to achieve classical control due to its scalable nature and overall miniaturization opportunities. Cryo-CMOS circuits and systems need to be carefully designed to ensure strict power budgets, while achieving quite advanced specifications in terms of noise and bandwidth. We review the requirements of a classical controller and cryo-CMOS circuits and systems developed for spin qubits in our lab. Results and perspectives are presented with a discussion about a road map for the future.
Quantum computers hold the promise to solve some of the most complex problems of today. The core of a quantum computer is a quantum processor, which is composed of quantum bits (qubits). Qubits are fragile and their state needs to be corrected in real time by a classical controller. Today, the control of qubits is done at room temperature by racks of instruments, while qubits operate at several tens of milli-Kelvin. To ensure compactness, and eventually scalability, we have proposed the use of controllers operating at a few Kelvin, so as to reduce the length of control cables, while potentially enabling superconductive interconnects, which enable virtually zero resistance and low thermal conductivity. We have chosen CMOS to achieve this functionality due to its scalable nature and overall miniaturization opportunities. Cryogenic CMOS, or cryo-CMOS, circuits and systems need to be carefully designed, so as to ensure low noise and high bandwidth, while operating at strict power budgets of a few milliwatts per qubit. In this paper, we outline the requirements of a classical controller and we show examples of such circuits and systems. Results and perspectives are presented discussing a roadmap for the future.
Future error-corrected quantum computers will require analog/mixed-signal control systems capable of providing a million or more high-precision analog waveforms. In this article, we begin by introducing the reader to superconducting transmon qubit technology and then explain how the state of a quantum processor implemented in this technology is controlled. By example, we then show how one can implement one part of the quantum control system as a cryogenic integrated circuit and review experimental results from the characterization of such an IC. The article concludes with a discussion of analog/mixed-signal design challenges that must be overcome in order to build the system required to control a million-qubit quantum computer.