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IEEE Electronics Packaging Technology Conference (EPTC)

Glass Substrate Interposer for TSV-integrated Surface Electrode Ion Trap

Peng Zhao, Hong Yu Li, Yu Dian Lim, Jing Tao, Wen Wei Seit, Luca Guidoni, Chuan Seng Tan

Published Dec 2, 2020• 11 citations
Publisher

Abstract

To facilitate large-scale implementation of quantum information processing (QIP) based on ion trap system, the design of through silicon via (TSV) integrated ion trap with glass interposer is proposed. Glass interposer is employed for TSV landing and to provide another degree of freedom for electrical signal delivery by the redistribution layer (RDL) on it. Benefited from the insulating property of glass, the parasitic capacitance between electrodes of glass interposer (0.4 pF) is significantly reduced, as compared to its silicon counterparts (650 pF). From the modeling, it is also shown that the reflection loss can be reduced by more than 30 dB when the silicon interposer is replaced by glass interposer. High power efficiency and low heat dissipation can thus be guaranteed during ion trapping operation.

DOI
10.1109/eptc50525.2020.9315003

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To facilitate large-scale implementation of quantum information processing (QIP) based on ion trap system, the design of through silicon via (TSV) integrated ion trap with glass interposer is proposed. Glass interposer is employed for TSV landing and to provide another degree of freedom for electrical signal delivery by the redistribution layer (RDL) on it. Benefited from the insulating property of glass, the parasitic capacitance between electrodes of glass interposer (0.4 pF) is significantly reduced, as compared to its silicon counterparts (650 pF). From the modeling, it is also shown that the reflection loss can be reduced by more than 30 dB when the silicon interposer is replaced by glass interposer. High power efficiency and low heat dissipation can thus be guaranteed during ion trapping operation.
In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compatible back-end-of-line process is employed on 300 mm silicon/glass wafer platform. Due to the incorporation of TSVs into ion trap design, the footprint of ion trap is reduced. Correspondingly, low parasitic capacitance (3 pF) and RF loss (insertion loss of -0.1 dB at frequency of 50 MHz) are achieved, presenting significant improvement than conventional trap that uses wire bonding as interconnections. The trap with reduced footprint also enables small-beam laser addressing. The obtained ion lifetime and heating rate are comparable with traps of similar dimension that operated in room temperature. Two solutions to mitigate trap heating issue are proposed. This heterogenous integrated ion trap is an important building block for scalable quantum information processing based on ion trap device.
Surface electrode ion trap is a promising candidate for quantum information processing (QIP), due to its feasibilities towards large-scale fabrication and on-chip electro-optical integration. In this paper, surface electrode ion traps on different substrates (e.g., high-resistivity silicon, silicon with ground plane and glass) are fabricated, assembled and tested. To simultaneously leverage the established fabrication technique of silicon and superior insulation property of glass, we further demonstrate a novel ion trap design with heterogenous integration of silicon and glass, acting respectively as ion trap and interposer substrates. The vertical connection between the silicon ion trap and the glass interposer is achieved by through silicon via (TSV) and micro bump. This silicon-glass integrated system advances the development of ion trap and enriches the toolbox of scalable QIP.
In this study, we report about the design, fabrication, and operation of a Cu-filled through-silicon via (TSV)-integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between an ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrode numbers and evolving complexity. The integration of TSVs reduces the form factor of the ion trap by more than 80%, minimizing parasitic capacitance from 32 ± 2 to 3 ± 0.2 pF. A low RF dissipation is achieved in spite of the absence of the ground screening layer. The entire fabrication process is on a 12-in. wafer and compatible with the established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (∼30 min) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
Surface electrode ion trap with through-silicon-via (TSV) integration enables 3D stacking of ion trap chip on an interposer to eliminate the wire-bonds on the surface electrodes and also addresses the challenge of the ever increasing complexity of surface electrode design with low-parasitic and high-density interconnect requirements. In this work, we demonstrate the design and fabrication of TSV integrated surface electrode ion trap on a 300-mm Si wafer platform. By designing the TSV arrays directly underneath the surface electrodes, the surface electrode foot print is reduced and the TSV traps show better RF performance compared to the planar traps with wire-bonding pads.
Further miniaturization of surface electrode ion trap is restricted by wire bonding connection. To resolve this restriction, integration of conventional surface electrode ion trap with through silicon via (TSV) interconnects is proposed and preliminarily demonstrated. Located directly underneath the DC and RF electrodes, TSVs can transmit the electrical signal from interposer to the electrodes on the top. In this work, electrostatic simulation and fabrication processes are introduced to justify the feasibility of this integration. From the electrical characterization (I-V and C-V tests) results, TSV-integrated ion trap exhibits smaller leakage current and lower capacitance than its wire bonding counterparts due to the elimination of large surface area.