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Symmetry-protected adiabatic quantum transistors

Dominic J. Williamson

Published Mar 1, 2014• 6 citations
OpenAlex

Abstract

The standard circuit model of quantum computation differs in principle from a modern day computer chip in that computation is brought to stationary qubits in the former whereas information is routed spatially across a chip by transistors in the latter. Recently a model was proposed that addresses this key difference in implementation, it was dubbed the adiabatic quantum transistor model to emphasise its similarity to a classical transistor. Here we generalise this model to the setting of spin chains in inherently quantum phases of matter with a property called symmetry-protected order. Our generalisation is significant as it shows the computational properties of the model persist robustly throughout each symmetry-protected quantum phase of matter.

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The standard circuit model of quantum computation differs in principle from a modern day computer chip in that computation is brought to stationary qubits in the former whereas information is routed spatially across a chip by transistors in the latter. Recently a model was proposed that addresses this key difference in implementation, it was dubbed the adiabatic quantum transistor model to emphasise its similarity to a classical transistor. Here we generalise this model to the setting of spin chains in inherently quantum phases of matter with a property called symmetry-protected order. Our generalisation is significant as it shows the computational properties of the model persist robustly throughout each symmetry-protected quantum phase of matter.
Adiabatic quantum transistors (AQT) allow quantum logic gates to be performed by applying a large field to a quantum many-body system prepared in its ground state, without the need for local control. The basic operation of such a device can be viewed as driving a spin chain from a symmetry-protected (SP) phase to a trivial phase. This perspective offers an avenue to generalize the AQT and to design several improvements. The performance of quantum logic gates is shown to depend only on universal symmetry properties of a SP phase rather than any fine tuning of the Hamiltonian, and it is possible to implement a universal set of logic gates in this way by combining several different types of SP matter. Such SP AQTs are argued to be robust to a range of relevant noise processes.
Abstract. While solid-state devices offer naturally reliable hardware for modern classical computers, thus far quantum information processors resemble vacuum tube computers in being neither reliable nor scalable. Strongly correlated many body states stabilized in topologically ordered matter offer the possibility of naturally fault tolerant computing, but are both challenging to engineer and coherently control and cannot be easily adapted to different physical platforms. We propose an architecture which achieves some of the robustness properties of topological models but with a drastically simpler construction. Quantum information is stored in the symmetry-protected degenerate ground states of spin-1 chains, while quantum gates are performed by adiabatic non-Abelian holonomies using only single-site fields and nearest-neighbor couplings. Gate operations respect the symmetry, and so inherit some protection from noise and disorder from the symmetry-protected ground states. ar X iv
This work introduces and characterizes quantum sequential circuits (QSCs) as a hardware-oriented paradigm for quantum computing, built upon a novel foundational element termed the quantum transistor. Unlike conventional qubit-based architectures, QSCs employ symmetry-protected topological junctions where quantum gates are encoded as Choi states via channel-state duality and activated through bulk measurements, utilizing ebits to realize the functional analog of feedback loops in classical sequential circuits. This framework establishes a universal model for quantum computation that inherently incorporates memory and temporal sequencing, complementing existing combinational quantum circuit model. Our work advances the conceptual bridge towards a quantum von Neumann architecture, underscoring the potential of hybrid and modular design principles for the development of large-scale, integrated quantum information processors.
While solid-state devices offer naturally reliable hardware for modern classical computers, thus far quantum information processors resemble vacuum tube computers in being neither reliable nor scalable. Strongly correlated many body states stabilized in topologically ordered matter offer the possibility of naturally fault tolerant computing, but are both challenging to engineer and coherently control and cannot be easily adapted to different physical platforms. We propose an architecture which achieves some of the robustness properties of topological models but with a drastically simpler construction. Quantum information is stored in the symmetry-protected degenerate ground states of spin-1 chains, while quantum gates are performed by adiabatic non-Abelian holonomies using only single-site fields and nearest-neighbor couplings. Gate operations respect the symmetry, and so inherit some protection from noise and disorder from the symmetry-protected ground states.
In this work, we propose and study in depth a universal quantum computing architecture based on a quantum construction of transistors. Our teleportation-based quantum transistors, called ``telesistors'', are ground states of systems with symmetry-protected topological order, hence suppress certain noises and provide high-fidelity Clifford gates without the need for active error correction. This physical protection, quantified by the string order parameters, serves as a low-overhead foundation upon which conventional fault-tolerant encoding (e.g., with stabilizer codes) can be built to achieve universal quantum computation. This architecture shows rich connections with current known architectures, and some desirable merits especially compared with the qubit-based circuits regarding modularity, integration, and program storage. Our study shows that it is plausible to realize it with current technology in the near future.