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APL Photonics

An optical chip for self-testing quantum random number generation

Nicolò Leone, Davide Rusca, Stefano Azzini, Giorgio Fontana, Fabio Acerbi, Alberto Giacomo Gola, Alessandro Tontini, Nicola Massari, Hugo Zbinden, Lorenzo Pavesi

Published Oct 1, 2020• 21 citations
Publisher

Abstract

We present an implementation of a semi-device-independent protocol of the generation of quantum random numbers in a fully integrated silicon chip. The system is based on a prepare-and-measure scheme, where we integrate a partially trusted source of photons and an untrusted single photon detector. The source is a silicon photomultiplier, which emits photons during the avalanche impact ionization process, while the detector is a single photon avalanche diode. The proposed protocol requires only a few and reasonable assumptions on the generated states. It is sufficient to measure the statistics of generation and detection in order to evaluate the min-entropy of the output sequence, conditioned on all possible classical side information. We demonstrate that this protocol, previously realized with a bulky laboratory setup, is totally applicable to a compact and fully integrated chip with an estimated throughput of 6 kHz of the certified quantum random bit rate.

DOI
10.1063/5.0022526

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We present an implementation of a semi-device-independent protocol of the generation of quantum random numbers in a fully integrated silicon chip. The system is based on a prepare-and-measure scheme, where we integrate a partially trusted source of photons and an untrusted single photon detector. The source is a silicon photomultiplier, which emits photons during the avalanche impact ionization process, while the detector is a single photon avalanche diode. The proposed protocol requires only a few and reasonable assumptions on the generated states. It is sufficient to measure the statistics of generation and detection in order to evaluate the min-entropy of the output sequence, conditioned on all possible classical side information. We demonstrate that this protocol, previously realized with a bulky laboratory setup, is totally applicable to a compact and fully integrated chip with an estimated throughput of 6 kHz of the certified quantum random bit rate.
We present a semi-device-independent quantum random number generator (QRNG) based on the violation of a contextuality inequality, implemented by the integration of two silicon photonic chips. Our system combines a heralded single-photon source with a reconfigurable interferometric mesh to implement qutrit state preparation, transformations, and measurements suitable for testing a KCBS contextuality inequality. This architecture enables the generation of random numbers from the intrinsic randomness of single-photon interference in a complex optical network, while simultaneously allowing a quantitative certification of their security without requiring entanglement. We observe a contextuality violation exceeding the classical bound by more than 10σ, unambiguously confirming non-classical behavior. From this violation, we certify a conditional min-entropy per experimental round of Hmin = 0.077 +- 0.002, derived via a tailored semidefinite-programming-based security analysis. Each measurement outcome therefore contains at least 0.077 +- 0.002 bits of extractable genuine randomness, corresponding to an asymptotic generation rate of 21.7 +- 0.5 bits/s. These results establish a viable route towards general-purpose, untrusted quantum random number generators compatible with practical integrated photonic quantum networks.
We present a new compact photonic quantum random number generator based on an emitter (source of entropy) and a single-photon detector integrated in the same silicon chip. Not only they are integrated one close to the other, but also they are fabricated with the same fabrication process. The emitter is a small silicon photomultiplier, composed of passively-quenched single photon avalanche diodes (SPADs), having the same layout of the single SPAD used as the detector. The emitter is a reverse-biased silicon p-n junction, generating photons mainly due to impact ionization during the avalanche breakdown process. The detector is shielded from ambient light by a top metal layer: only photons from the emitter are detected, making this integrated approach more robust. The random bits are extracted with a robust methodology based on the measurement of photon arrival times, using discrete time bins, in a time frame cyclically repeated in time. No postprocessing is required for the raw data to pass the statistical tests.
The power of quantum random number generation is more than just the ability to create truly random numbers—it can also enable , which allows the user to verify the implementation integrity of critical quantum components with minimal assumptions. In this work, we develop and implement a self-testing quantum random number generator (QRNG) chipset capable of generating 15.33 Mbits of certifiable randomness in each run, producing an expansion rate of 5.11 × 10 − 4 at a repetition rate of 10 MHz, with quantum side information considered for a high level of security. The chip design is based on a highly loss-and-noise-tolerant measurement-device-independent protocol, where random coherent states encoded using quadrature phase shift keying are used to self-test the integrated homodyne detectors—well-known to be challenging to characterize in practice. Importantly, this proposal opens up the possibility of implementing miniaturized self-testing QRNG devices at production scale using standard silicon photonics foundry platforms.
In this paper, a nondeterministic random number generator based on detection of the single photons emitted by an Si-CMOS-LED light source integrated for the first time on the detector chip is presented and experimentally demonstrated. We use a ring-shaped single-photon avalanche diode (SPAD) around the Si-CMOS-LED fabricated in 0.35-μm HV-CMOS technology to generate random events. The time intervals between single-photon events are independent quantum random variables. A field-programmable gate array (FPGA) digitizes the time variables to the stream of random bits. Bias in the raw data due to the nonuniform distribution of the time intervals is removed by postprocessing in a special configuration of xor gates to improve the randomness of the generated random bits. The quantum random numbers in 1-Gb streams with bit generation rate of 1 Mb/s were directly delivered to a personal computer (PC) and passed all statistical tests from ENT, STS, and DIEHARD, as well as for more accuracy correlation and bias tests applied on these streams.
A compact quantum random number generator (QRNG) based on an array of Single Photon Avalanche Diodes (SPADs) is presented here. The main feature of the proposed chip is the capability to generate random numbers without the use of any external source of light. In this view, SPADs are configured to be used in two ways: 1) as a controlled light emitter and 2) as a detector. An embedded logic is able to distinguish dark events against detected emitted photon in such a way to make the system sensitive only to the presence of light. The extracted random bits show a uniform distribution and the QRNG, thanks to an integrated conditioning block maximizing the output entropy, eventually passes all AIS31 tests. The average raw bit rate in the default device configuration (one enabled column) is measured equal to 800 kbps.
We introduce a scheme for a self-testing quantum random-number generator and demonstrate it experimentally. Compared to the fully device-independent model, our scheme requires an extra natural assumption, namely, that the mean number of photons of the signal optical modes is bounded. The scheme is self-testing, as it allows the user to verify in real time the correct functioning of the setup, hence guaranteeing the continuous generation of certified random bits. The scheme is based on a prepare-and-measure setup, which we implement in a proof-of-principle experiment using only off-the-shelf optical components. The randomness generation rate is 1.25 Mbits/s, comparable to commercial solutions. Overall, we believe that this scheme achieves a promising trade-off between the required assumptions, ease of implementation and performance.