Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Quantum Information and Computation

Efficient reversible quantum design of sig-magnitude to two's complement converters

Francisco José Orts, Gloria Ortega, Ester Martín Garzón

Published Aug 1, 2020• 2 citations
Publisher

Abstract

Despite the great interest that the scientific community has in quantum computing, the scarcity and high cost of resources prevent to advance in this field. Specifically, qubits are very expensive to build, causing the few available quantum computers are tremendously limited in their number of qubits and delaying their progress. This work presents new reversible circuits that optimize the necessary resources for the conversion of a sign binary number into two's complement of N digits. The benefits of our work are two: on the one hand, the proposed two's complement converters are fault tolerant circuits and also are more efficient in terms of resources (essentially, quantum cost, number of qubits, and T-count) than the described in the literature. On the other hand, valuable information about available converters and, what is more, quantum adders, is summarized in tables for interested researchers. The converters have been measured using robust metrics and have been compared with the state-of-the-art circuits. The code to build them in a real quantum computer is given.

DOI
10.26421/qic20.9-10-3

Related papers

Efficient design of a quantum absolute-value circuit using Clifford+T gates

Francisco José Orts, Gloria Ortega, Elías F. Combarro +3 more

Abstract Current quantum computers have a limited number of resources and are heavily affected by internal and external noise. Therefore, small, noise-tolerant circuits are of great interest. With regard to circuit size, it is especially important to reduce the number of required qubits. Concerning to fault-tolerance, circuits entirely built with Clifford+T gates allow the use of error correction codes. However, the T-gate has an excessive cost, so circuits with a high number of T-gates should be avoided. This work focuses on optimising in such terms an operation that is widely used in larger circuits and algorithms: the calculation of the absolute-value of two’s complement encoded integers. The proposed circuit halves the number of required T gates with respect to the best circuit currently available in the literature. Moreover, our circuit requires at least 2 qubits less than the other circuits for such an operation.

The Journal of Supercomputing•Mar 18, 2023•6 citations

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder

Sheba Diamond Thabah, Prabir Saha

The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.

Periodica Polytechnica Electrical Engineering and Computer Science•Sep 14, 2020•2 citations

A Resource-Efficient Design for a Reversible Floating Point Adder in Quantum Computing

Trung Duc Nguyen, Rodney Van Meter

Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The KQ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

ACM Journal on Emerging Technologies in Computing Systems•Nov 18, 2014•20 citations

Novel Quaternary Quantum Reversible Half Adder and Full Adder Circuits

Abdollah Norouzi Doshanlou, Majid Haghparast, Mehdi Hosseinzadeh

One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.

IETE Journal of Research•Aug 29, 2019•12 citations

Design and Development of Cost Optimized Quantum Binary-Coded Decimal Adder using Reversible Logic Gates

Parna Kundu, Mousom Chatterjee, Susmita Biswas +6 more

Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.

ES General•Jan 1, 2025•0 citations

Quantum Arithmetic for Real-Number 2’s Complement Multiplication

Wiwat Asawalertsak, Rajchawit Sarochawikasit, Prapong Prechaprapranwong

In classical computing, 2’s complement representation is essential for handling signed binary arithmetic, enabling efficient operations for both positive and negative numbers. However, many quantum multiplication circuits typically lack native support for 2’s complement, limiting their application to signed arithmetic tasks. Prior quantum multiplication algorithms capable of handling 2’s complement often demand an impractically large number of qubits. This paper introduces 3 novel quantum circuit designs for real-number 2’s complement multiplication, inspired by classical signed multiplication algorithms. These designs achieve a quadratic time complexity, comparable to RCA-based quantum unsigned multiplication algorithms, while significantly reducing qubit requirements compared to prior quantum signed multiplication schemes. The first model requires the largest number of qubits but applies to a broad range of cases; the second uses fewer qubits but requires specific multiplier conditions; and the third uses the fewest qubits but operates under stricter multiplier constraints and circuit positioning conditions. Benchmarking results demonstrate their ability to perform 2’s complement multiplication correctly. This work advances qubit-efficient solutions, laying a foundation for further development of 2’s complement-based quantum algorithms.

International Conference on Quantum Communications, Networking, and Computing (QCNC)•Mar 31, 2025•0 citations
Despite the great interest that the scientific community has in quantum computing, the scarcity and high cost of resources prevent to advance in this field. Specifically, qubits are very expensive to build, causing the few available quantum computers are tremendously limited in their number of qubits and delaying their progress. This work presents new reversible circuits that optimize the necessary resources for the conversion of a sign binary number into two's complement of N digits. The benefits of our work are two: on the one hand, the proposed two's complement converters are fault tolerant circuits and also are more efficient in terms of resources (essentially, quantum cost, number of qubits, and T-count) than the described in the literature. On the other hand, valuable information about available converters and, what is more, quantum adders, is summarized in tables for interested researchers. The converters have been measured using robust metrics and have been compared with the state-of-the-art circuits. The code to build them in a real quantum computer is given.
Abstract Current quantum computers have a limited number of resources and are heavily affected by internal and external noise. Therefore, small, noise-tolerant circuits are of great interest. With regard to circuit size, it is especially important to reduce the number of required qubits. Concerning to fault-tolerance, circuits entirely built with Clifford+T gates allow the use of error correction codes. However, the T-gate has an excessive cost, so circuits with a high number of T-gates should be avoided. This work focuses on optimising in such terms an operation that is widely used in larger circuits and algorithms: the calculation of the absolute-value of two’s complement encoded integers. The proposed circuit halves the number of required T gates with respect to the best circuit currently available in the literature. Moreover, our circuit requires at least 2 qubits less than the other circuits for such an operation.
The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.
Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The KQ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.
One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
In classical computing, 2’s complement representation is essential for handling signed binary arithmetic, enabling efficient operations for both positive and negative numbers. However, many quantum multiplication circuits typically lack native support for 2’s complement, limiting their application to signed arithmetic tasks. Prior quantum multiplication algorithms capable of handling 2’s complement often demand an impractically large number of qubits. This paper introduces 3 novel quantum circuit designs for real-number 2’s complement multiplication, inspired by classical signed multiplication algorithms. These designs achieve a quadratic time complexity, comparable to RCA-based quantum unsigned multiplication algorithms, while significantly reducing qubit requirements compared to prior quantum signed multiplication schemes. The first model requires the largest number of qubits but applies to a broad range of cases; the second uses fewer qubits but requires specific multiplier conditions; and the third uses the fewest qubits but operates under stricter multiplier constraints and circuit positioning conditions. Benchmarking results demonstrate their ability to perform 2’s complement multiplication correctly. This work advances qubit-efficient solutions, laying a foundation for further development of 2’s complement-based quantum algorithms.