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International journal of advance research and innovative ideas in education

IMPLEMENTATION AND DESIGN OF BCD ADDER USING QUBIT GATES FOR QUANTUM APPLICATIONS

k.mahesh babu

Published Jan 1, 2019• 0 citations
OpenAlex

Abstract

Reversible Logic is an emerging technology, it has hellocious applications in various fields. Reversible logic implementation reduces loss of entropy because of bit manipulations. . In this work we present a novel design of reversible 2 DIGIT BCD ADDER using INTEGRATED QUBIT GATES. The reversible BCD adder is designed from 2*2 control V, Control V+, CNOT, MTSG,FREDKIN[4],FEYMAN ,INTEGRATED QUBIT GATES. The design of proposed reversible adder- requires minimum quantum cost ,delay by maintaining ancilla inputs and garbage outputs.

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Reversible Logic is an emerging technology, it has hellocious applications in various fields. Reversible logic implementation reduces loss of entropy because of bit manipulations. . In this work we present a novel design of reversible 2 DIGIT BCD ADDER using INTEGRATED QUBIT GATES. The reversible BCD adder is designed from 2*2 control V, Control V+, CNOT, MTSG,FREDKIN[4],FEYMAN ,INTEGRATED QUBIT GATES. The design of proposed reversible adder- requires minimum quantum cost ,delay by maintaining ancilla inputs and garbage outputs.
Reversible Logic is an emerging technology; it has hellocious applications in various fields. Reversible logic implementation reduces loss of entropy because of bit manipulations. . In this work we present a novel design of reversible 2 DIGIT BCD ADDER using INTEGRATED QUBIT GATES. The reversible BCD adder is designed from 2*2 control V, Control V+, CNOT, MTSG,FREDKIN(4),FEYMAN, INTEGRATED QUBIT GATES (1).The design of proposed reversible adder- requires minimum quantum cost ,delay by maintaining ancilla inputs and garbage outputs.
Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest quantum cost value. Other parameters such as ancilla input, garbage output and delay are kept at minimal. Experiment result shows that the proposed work outperforms other designs in terms of quantum cost. Considering for a 1 digit BCD adder, it has a 4% improvement in terms of quantum cost compared to the current best existing ones. The improvement range increases as the BCD digit becomes larger.
Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V+ gates. The present work presents Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.
Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word.Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design.The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V + gates.The present work presents parallel adder/subtractor (with over flow detection), as well as Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.