Hardware-Centric Quantum Computing for Noisy Systems

Merel A. Schalkers, Matthias Möller

Shengwang Du

Quantum computing promises transformative advances in computation, communication, sensing, and machine learning. Yet the realization of large-scale fault-tolerant quantum computers remains hindered by the enormous overhead required for quantum error correction. This challenge raises a fundamental question: Must useful quantum computing wait until fully fault-tolerant quantum hardware becomes available? In this Perspective, we propose Recoverable Quantum Computation (RQC), an information-centric paradigm for quantum computing with errors. Rather than requiring faithful preservation of the complete quantum state, RQC focuses on preserving the computational information required to accomplish a given task. A quantum computation is considered recoverable if the desired computational information can be extracted from noisy quantum outputs with an overhead that preserves quantum advantage relative to the best known classical method. We introduce recoverability as an operational principle for evaluating noisy quantum computations and propose practical metrics based on recovery overhead and recoverability efficiency. We illustrate the framework using quantum Fourier transform period estimation on IBM quantum hardware and a conceptual example from quantum machine learning, demonstrating that useful computational information may remain recoverable despite significant physical errors. Building on these examples, we propose a preliminary classification of quantum applications according to their expected recoverability and outline a research roadmap toward a predictive theory of recoverability. RQC is intended not as an alternative to fault-tolerant quantum computing, but as a complementary paradigm for understanding and evaluating useful quantum computation in the broad intermediate regime between today's noisy quantum processors and tomorrow's fault-tolerant quantum computers.

Emanuel H. Knill

Simon Martiel, Thomas Ayral, Cyril Allouche

Existing protocols for benchmarking current quantum coprocessors fail to meet the usual standards for assessing the performance of high-performance-computing platforms. After a synthetic review of these protocols—whether at the gate, circuit, or application level—we introduce a new benchmark, dubbed Atos Q-score, which is application-centric, hardware-agnostic, and scalable to quantum advantage processor sizes and beyond. The Q-score measures the maximum number of qubits that can be usedeffectivelyto solve the MaxCut combinatorial optimization problem with the quantum approximate optimization algorithm. We give a robust definition of the notion of effective performance by introducing an improved approximation ratio based on the scaling of random and optimal algorithms. We illustrate the behavior of Q-score using perfect and noisy simulations of quantum processors. Finally, we provide an open-source implementation of Q-score that makes it easy to compute the Q-score of any quantum hardware.

Keren Li

Utkarsh Azad, Ankit Papneja, Rakesh Kumar Saini +2 more

Abstract With the development in the field of quantum physics, several methods for building a quantum computer have emerged. These differ in qubit technologies, interaction topologies, and noise characteristics. In this article, insights are given into the circuit‐centric architecture design of Noisy Intermediate‐Scale Quantum (NISQ) devices. The dependence of the circuit size, circuit depth on the interaction and connection between different qubits present in quantum hardware are discussed. A noise‐aware procedure is presented which helps in determining the optimal interactions between different qubits of a quantum chip to execute a given circuit in the most efficient way possible. In this article, the 5‐qubit hardware in a noiseless setting is illustrated with an example. Also, a benchmark‐driven analysis is performed to show the importance of noise adaptivity in determining the hardware reliability. It is concluded that a generalized and flexible procedure such as this approach can aid in determining the design of hardware accurately for which the circuit runs efficiently, that is, with the least number of clock cycles, the lowest gate operations, and noise‐based errors.