Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

Hardware-Aware Sum-Product Decoding in the Decision Domain

Mizuki YAMADA, Keigo Takeuchi, Kiyoyuki KOIKE

Published Dec 1, 2019• 0 citations
Publisher

Abstract

We propose hardware-aware sum-product (SP) decoding for low-density parity-check codes. To simplify an implementation using a fixed-point number representation, we transform SP decoding in the logarithm domain to that in the decision domain. A polynomial approximation is proposed to implement an update rule of the proposed SP decoding efficiently. Numerical simulations show that the approximate SP decoding achieves almost the same performance as the exact SP decoding when an appropriate degree in the polynomial approximation is used, that it improves the convergence properties of SP and normalized min-sum decoding in the high signal-to-noise ratio regime, and that it is robust against quantization errors.

DOI
10.1587/transfun.e102.a.1980

Related papers

An improved implementation of sum-product algorithm for LDPC decoder

Zhou Wang, Bin Wu, Tianchun Ye

An improved decoding algorithm for low-density parity-check (LDPC) codes is presented. By taking advantages of the first-term Taylor’s series multiple expansion to approximate the correction term of the Jacobian logarithm used in LLR-SPA (log-likelihood ratio sum-product algorithm), we propose an algorithm which significantly simplifies the check node update computation of the optimal LLR-SPA. Besides, the parameter δ is introduced to determine suitable expansion points. The simulation result shows that the proposed method with ten expansion points when δ is set to 0.01 has almost identical performance compared with ideal SPA algorithm and outperforms both the min-sum algorithm (MS), the offset min-sum algorithm (OMS) and the normalised min-sum algorithm (NMS). The architecture of proposed method is also presented for implementation, which has reduced computational complexity and is feasible for hardware implementation.

IEICE Electronics Express•Jan 1, 2019•3 citations

Simplified sum-product algorithm using piecewise linear function approximation for low complexity LDPC decoding

Jae Hee Han, Myung Hoon Sunwoo

This paper proposes the simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes (LDPC). The sum-product algorithm achieves the highest BER performance among the LDPC decoding algorithms. However, based on the hyperbolic tangent and inverse hyperbolic tangent functions for the check node updates, the sum-product (SP) algorithm requires high computational complexity. To reduce computational complexity, the proposed SSP algorithm adopts a piecewise linear approximation, the logarithmic and exponential functions, which can replace multiplications and divisions with additions and subtractions. In addition, the proposed SSP algorithm can simplify both the ln[tanh(x)] and tanh-1[exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Simulation results show that the proposed SSP algorithm can improve about 0.8 dB of bit error ratio (BER) performance compared with the modified sum-product algorithm.

International Conference on Ubiquitous Information Management and Communication (IMCOM)•Feb 15, 2009•7 citations

New sum-product algorithm using approximation method for low complexity LDPC decoding

Jae Hee Han, Myung Hoon Sunwoo

This paper proposes a new sum-product algorithm to improve BER performance for low-density parity-check codes. The proposed algorithm can replace multiplications and divisions with additions and subtractions by adding the logarithmic and exponential functions. In addition, the proposed algorithm can simplify both the ln[tanh(x)] and tanh-1[exp(x)] functions by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SP algorithm can improve maximum of 0.8 dB BER performance compared with the existing modified sumproduct algorithm.

International SoC Design Conference•Nov 1, 2008•1 citation

Low complexity LDPC decoder with modified Sum-Product algorithm

Chen Qian, Weilong Lei, Zhaocheng Wang

This paper describes an efficient implementation of the Sum-Product Algorithm (SPA) within a Low Density Parity Check (LDPC) code decoder, where a horizontal process correction term is used to improve the decoding performance of the Min-Sum algorithms. The correction term is implemented as a look-up table. The algorithm uses the correction term redundancy by means of a coordinate transformation to reduce the hardware complexity. Simulations and hardware tests indicate that the decoding performance is very good with the appropriate look-up table.

Tsinghua Science & Technology•Feb 1, 2013•11 citations

Efficient implementations of the sum-product algorithm for decoding LDPC codes

Xiao-Yu Hu, Evangelos S. Eleftheriou, D.-M. Arnold +1 more

Efficient implementations of the sum-product algorithm (SPA) are presented for decoding low-density parity-check (LDPC) codes using log-likelihood ratios (LLR) as messages between symbol and parity-check nodes. Various reduced-complexity derivatives of the LLR-SPA are proposed. Both serial and parallel implementations are investigated, leading to trellis and tree topologies, respectively. Furthermore, by exploiting the inherent robustness of LLRs, it is shown, via simulations, that coarse quantization tables are sufficient to implement complex core operations with negligible or no loss in performance. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate design point in high-speed applications from a performance, latency and computational complexity perspective.

Globecom•Nov 13, 2002•375 citations

Efficient implementation of the sum-product algorithm forquantized decoding of LDPC codes

Wang Xin-meii

An efficient implementation of the Sum-Product algorithm(SPA) in the log-likelihood ratio (LLR) domain is presented in [1]. In this paper, We modify a formula in [1] such that SPA can be implemented by using two small look-up tables. With this modification, all the calculations involved in this implementation involve only additions, subtractions, comparisons and table looking-ups, which leads to low computation complexity and facility in hardware implementation. Based on this modified implementation, various quantization schemes of SPA for decoding low-density parity-check (LDPC) codes are investigated. And the issues related to quantization, such as clipping levels and variables quantization, are also investigated. Simulation results show that the performance of the uniform quantization scheme is very close to that of the non-quantizaiton over the AWGN channel. Moreover, it can obtain the same performance as that of non-quantization at high SNRs.

Journal of Xidian University•Jan 1, 2004•0 citations
We propose hardware-aware sum-product (SP) decoding for low-density parity-check codes. To simplify an implementation using a fixed-point number representation, we transform SP decoding in the logarithm domain to that in the decision domain. A polynomial approximation is proposed to implement an update rule of the proposed SP decoding efficiently. Numerical simulations show that the approximate SP decoding achieves almost the same performance as the exact SP decoding when an appropriate degree in the polynomial approximation is used, that it improves the convergence properties of SP and normalized min-sum decoding in the high signal-to-noise ratio regime, and that it is robust against quantization errors.
An improved decoding algorithm for low-density parity-check (LDPC) codes is presented. By taking advantages of the first-term Taylor’s series multiple expansion to approximate the correction term of the Jacobian logarithm used in LLR-SPA (log-likelihood ratio sum-product algorithm), we propose an algorithm which significantly simplifies the check node update computation of the optimal LLR-SPA. Besides, the parameter δ is introduced to determine suitable expansion points. The simulation result shows that the proposed method with ten expansion points when δ is set to 0.01 has almost identical performance compared with ideal SPA algorithm and outperforms both the min-sum algorithm (MS), the offset min-sum algorithm (OMS) and the normalised min-sum algorithm (NMS). The architecture of proposed method is also presented for implementation, which has reduced computational complexity and is feasible for hardware implementation.
This paper proposes the simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes (LDPC). The sum-product algorithm achieves the highest BER performance among the LDPC decoding algorithms. However, based on the hyperbolic tangent and inverse hyperbolic tangent functions for the check node updates, the sum-product (SP) algorithm requires high computational complexity. To reduce computational complexity, the proposed SSP algorithm adopts a piecewise linear approximation, the logarithmic and exponential functions, which can replace multiplications and divisions with additions and subtractions. In addition, the proposed SSP algorithm can simplify both the ln[tanh(x)] and tanh-1[exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Simulation results show that the proposed SSP algorithm can improve about 0.8 dB of bit error ratio (BER) performance compared with the modified sum-product algorithm.
This paper proposes a new sum-product algorithm to improve BER performance for low-density parity-check codes. The proposed algorithm can replace multiplications and divisions with additions and subtractions by adding the logarithmic and exponential functions. In addition, the proposed algorithm can simplify both the ln[tanh(x)] and tanh-1[exp(x)] functions by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SP algorithm can improve maximum of 0.8 dB BER performance compared with the existing modified sumproduct algorithm.
This paper describes an efficient implementation of the Sum-Product Algorithm (SPA) within a Low Density Parity Check (LDPC) code decoder, where a horizontal process correction term is used to improve the decoding performance of the Min-Sum algorithms. The correction term is implemented as a look-up table. The algorithm uses the correction term redundancy by means of a coordinate transformation to reduce the hardware complexity. Simulations and hardware tests indicate that the decoding performance is very good with the appropriate look-up table.
Efficient implementations of the sum-product algorithm (SPA) are presented for decoding low-density parity-check (LDPC) codes using log-likelihood ratios (LLR) as messages between symbol and parity-check nodes. Various reduced-complexity derivatives of the LLR-SPA are proposed. Both serial and parallel implementations are investigated, leading to trellis and tree topologies, respectively. Furthermore, by exploiting the inherent robustness of LLRs, it is shown, via simulations, that coarse quantization tables are sufficient to implement complex core operations with negligible or no loss in performance. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate design point in high-speed applications from a performance, latency and computational complexity perspective.
An efficient implementation of the Sum-Product algorithm(SPA) in the log-likelihood ratio (LLR) domain is presented in [1]. In this paper, We modify a formula in [1] such that SPA can be implemented by using two small look-up tables. With this modification, all the calculations involved in this implementation involve only additions, subtractions, comparisons and table looking-ups, which leads to low computation complexity and facility in hardware implementation. Based on this modified implementation, various quantization schemes of SPA for decoding low-density parity-check (LDPC) codes are investigated. And the issues related to quantization, such as clipping levels and variables quantization, are also investigated. Simulation results show that the performance of the uniform quantization scheme is very close to that of the non-quantizaiton over the AWGN channel. Moreover, it can obtain the same performance as that of non-quantization at high SNRs.