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Wave Electronics and its Application in Information and Telecommunication Systems (WECONF)

Abouth Multi-Threshold Decoding of Low-Density Parity-Check Codes

Andrei A. Ovchinnikov, D. V. Ilina

Published Jun 1, 2019• 0 citations
Publisher

Abstract

Low-density parity-check codes are one of the most common forward error-correction techniques used in many existing and perspective standards including 5G wireless transmission standards and ultra-high-rate (400 Gbit/s and more) fiber-optic transmission standards. These codes should combine scalability of codelength from dozens to dozens of thousands bits and of coderate from low to very high with outstanding error-correcting performance when operating under severe practical limitations both from the point of view of decoding error and complexity issues. In many practical cases most widely used decoders suffer either from complexity out of system restrictions or from error performance penalties. In this paper the performance-complexity trade-off approach is considered, based on improved hard-decision decoders. Decoding of low-density parity-check codes with bit-flip algorithm is considered. The multi-threshold decoder based on the bit inversion algorithm is described using dynamically changed threshold during the decoding iterations, as well as the simplest empirical method is proposed for thresholds calculation. Simulation results in Gaussian channel with hard decision demodulation are given.

DOI
10.1109/weconf.2019.8840583

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Low-density parity-check codes are one of the most common forward error-correction techniques used in many existing and perspective standards including 5G wireless transmission standards and ultra-high-rate (400 Gbit/s and more) fiber-optic transmission standards. These codes should combine scalability of codelength from dozens to dozens of thousands bits and of coderate from low to very high with outstanding error-correcting performance when operating under severe practical limitations both from the point of view of decoding error and complexity issues. In many practical cases most widely used decoders suffer either from complexity out of system restrictions or from error performance penalties. In this paper the performance-complexity trade-off approach is considered, based on improved hard-decision decoders. Decoding of low-density parity-check codes with bit-flip algorithm is considered. The multi-threshold decoder based on the bit inversion algorithm is described using dynamically changed threshold during the decoding iterations, as well as the simplest empirical method is proposed for thresholds calculation. Simulation results in Gaussian channel with hard decision demodulation are given.
An improved iterative bit-flipping(BF) algorithm adapted for decoding low-density parity-check(LDPC) codes is proposed to improve the performance of the hard-decision BF decoding algorithm.The new algorithm uses an alternating threshold pattern to determine the bits whether to be flipped or not,and the flipping error probability is effectively decreased.Simulation results show that compared with BF algorithm,the improved BF algorithm improves both the error-correction performance and the convergence speed while maintaining the low computational complexity.
An improved bit-flipping(BF) algorithm with low complexity for decoding structured low-density parity-check codes(LDPC) is proposed to improve the performance of the hard-decision BF algorithm.The hard-decision bits are divided into two groups based on the magnitudes of the received symbols,and at each iteration,the proposed algorithm can flip more than one bit with using two thresholds,and the flipping error probability is effectively decreased.The improved BF algorithm requires some real number comparisons before iterations and requires only logical operations during the iterations.Compared with the weighted bit-flipping algorithm and its modifications,the new method is with significantly lower complexity.Simulations show that the proposed algorithm is provided with very fast convergence speed and excellent performance with significantly low complexity.
Decoding of low-density parity-check codes with bit-flip algorithm is considered. The majority-logic decoding is described as bit-flip algorithm with modified decoding threshold. The hybrid decoding combining both algorithms is considered and simulation results in Gaussian channel with hard decision demodulation are given. Described scheme may be effective in high-speed channels with low number of decoding iterations demands together with the requirements of low decoding error probabilities and low error-floors.
The bit-flipping (BF) algorithm for decoding of low-density parity-check (LDPC) codes requires less complex hardware than other decoding algorithms, but its error correcting performance needs to be improved. In this letter, a threshold adaptation scheme is applied to BF algorithm based decoding of LDPC codes. Our experiments show that the optimal threshold value for BF depends on the error conditions, and threshold adjustment during decoding helps to prevent meaningless no-flipping iterations. Based on these statistical observations, the adaptive threshold technique is proposed to pursue both the maximum error correcting capability and the fastest decoding convergence.
Low-density parity-check (LDPC) codes had a renaissance when they were rediscovered in the 1990’s. Since then LDPC codes have been an important part of the field of error-correcting codes, and have been shown to be able to approach the Shannon capacity, the limit at which we can reliably transmit information over noisy channels. Following this, many modern communications standards have adopted LDPC codes. Error-correction is equally important in protecting data from corruption on a hard-drive as it is in deep-space communications. It is most commonly used for example for reliable wireless transmission of data to mobile devices. For practical purposes, both encoding and decoding need to be of low complexity to achieve high throughput and low power consumption. This thesis provides a literature review of the current state-of-the-art in encoding and decoding of LDPC codes. Message- passing decoders are still capable of achieving the best error-correcting performance, while more recently considered bit-flipping decoders are providing a low-complexity alternative, albeit with some loss in error-correcting performance. An implementation of a low-complexity stochastic bit-flipping decoder is also presented. It is implemented for Graphics Processing Units (GPUs) in a parallel fashion, providing a peak throughput of 1.2 Gb/s, which is significantly higher than previous decoder implementations on GPUs. The error-correcting performance of a range of decoders has also been tested, showing that the stochastic bit-flipping decoder provides relatively good error-correcting performance with low complexity. Finally, a brief comparison of encoding complexities for two code ensembles is also presented.
Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. This reduces the amount of messages passed by the algorithm, which can be expected to reduce the switching activity of a hardware implementation. While direct application of the modification results in severe performance penalties, we show how to adapt the algorithm to reduce the impact, resulting in a negligible decrease in error correction performance.