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European Society for Fuzzy Logic and Technology Conference

Towards Memory Access Optimization in Quantum Computing

Mateus Nascimento, Anderson Ávila, Renata Reisen, Mauricio Lima Pilla

Published Jan 1, 2019• 0 citations
Publisher

Abstract

Due to the lack of quantum hardware, quantum simulation (QS) is still the most common method to study quantum computing.Due to the great number of operations and memory requirements, simulators should be properly built to efficiently explore modern classic computers.This work focuses on the memory access requirements that present a bottleneck not just for QS, but for computer science research as a whole.Our proposed methodology collaborates with the memory usage reduction, mitigating the effects of the memory wall.Our results show improvements in memory usage and the overall speed of circuit simulations.Our case test in the D-GM simulator with controlled operators, such as dense, primary and secondary diagonal patterns, showed an improvement for execution time in the order of 50 %.Our methodology can be applied not only in QS, but also for related applications with complex memory access patterns.

DOI
10.2991/eusflat-19.2019.65

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Due to the lack of quantum hardware, quantum simulation (QS) is still the most common method to study quantum computing.Due to the great number of operations and memory requirements, simulators should be properly built to efficiently explore modern classic computers.This work focuses on the memory access requirements that present a bottleneck not just for QS, but for computer science research as a whole.Our proposed methodology collaborates with the memory usage reduction, mitigating the effects of the memory wall.Our results show improvements in memory usage and the overall speed of circuit simulations.Our case test in the D-GM simulator with controlled operators, such as dense, primary and secondary diagonal patterns, showed an improvement for execution time in the order of 50 %.Our methodology can be applied not only in QS, but also for related applications with complex memory access patterns.
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As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.
Quantum circuit simulation is essential for researchers to develop and evaluate novel quantum algorithms with classical computers. Although full-state quantum circuit simulations are widely utilized for prototyping and debugging, they are computationally intensive due to the exponential growth in simulation time as the system size grows. To address the performance bottlenecks associated with conventional gate-by-gate simulation, this work refines the block-by-block simulation paradigm through blocking optimization, taking into account the architectural characteristics of hardware. The primary contribution of this research is the gate block search algorithm (GBSA), which efficiently groups the maximum number of quantum gates into gate blocks. This grouping technique enhances data reuse and reduces redundant memory accesses and I/O overhead during gate application. The proposed method is evaluated using both gate-level and circuit-level benchmarks on an AMD 64-core processor. Compared to conventional gate-by-gate simulators, such as QuEST and AerSimulator, the proposed approach achieves up to a 4.7× speedup in CPU execution and a 2.9× speedup in SSD-based scenarios. Furthermore, it can lead to a remarkable 46× reduction in memory and I/O traffic. These results indicate that the proposed block-based simulation strategy substantially improves the efficiency of quantum circuit simulation and can be readily adapted to multi-device environments, thereby supporting the rapid development of next-generation quantum algorithms.
Software quantum simulators are essential tools for designing and testing quantum algorithms on classical computing architectures, especially given the current limitations of physical quantum hardware. This work focuses on studying and evaluating memory management strategies for scalable quantum state simulation. We examine full-state representation, dynamic state pruning, shared-memory parallelization with OpenMP, distributed memory execution using MPI, and error-bounded floating-point compression with ZFP. These techniques are implemented in a prototype simulator and assessed using the quantum Fourier transform as a benchmark, with performance compared against leading open-source simulators such as Intel-QS, QuEST, and qsim. The results show the trade-offs between computational overhead and memory efficiency, and demonstrate that hybrid approaches combining distributed memory and compression can significantly extend the number of qubits that can be simulated. This work contributes practical insights for improving the scalability of software quantum simulators on classical hardware through optimized memory usage.
Quantum computing has shown great potential in addressing traditional computational challenges, but due to its high error rates and noise issues, classical simulation has become an essential tool for verifying its performance. However, the superposition and entanglement properties of quantum systems pose significant challenges for simulation, especially when memory is limited. Although circuit cutting methods can decompose large-scale quantum circuits into smaller computational tasks to reduce computational load, previous research primarily focused on their application to quantum computers, without fully considering their effectiveness in quantum circuit simulation. This study fills that gap by proposing an optimization scheme based on a heuristic cutting algorithm and subcircuit state vector reuse to address memory limitations in simulations. By incorporating global computational cost considerations and an integer programming model, the heuristic method proposed in this paper not only optimizes the cutting process but also combines subcircuit state vector reuse to reduce redundant calculations and memory usage. Experimental results show that compared to current popular circuit cutting methods, the proposed approach significantly improves simulation speed while reducing memory requirements, effectively addressing the challenges in quantum circuit simulation. The overall average speedup achieved 46%.
Exponential increase and global access to read/write memory states in quantum computing (QC) simulation limit both the number of qubits and quantum transformations which can be currently simulated. Although QC simulation is parallel by nature, spatial and temporal complexity are major performance hazards, making this a nontrivial application for high performance computing. A new methodology employing reduction and decomposition optimizations has shown relevant results, but its GPU implementation could be further improved. In this work, we develop a new kernel for in situ GPU simulation that better explores its resources without requiring further hardware. Shor’s and Grover’s algorithms are simulated up to 25 and 21 qubits respectively and compared to our previous version, to [Formula: see text] simulator and to ProjectQ framework, showing better results with relative speedups up to 4.38×, 3357.76× and 333× respectively.