Placement, routing, and scheduling are essential tasks for near-optimal performance of programs for noisy quantum processors. Reliable execution of an arbitrary quantum circuit on current devices requires routing methods that overcome connectivity limitations while meeting data locality requirements. However, current devices also express highly variable noise levels in both the quantum gates and quantum registers. This requires any routing algorithm to be adaptive to both the circuit and the operating conditions. We demonstrate near-optimal routing methods of noisy quantum states that minimize the overall error of data movement while also limiting the computational complexity of routing decisions. We evaluate our methods against the noise characteristics of a 20-qubit superconducting quantum processor.
Placement, routing, and scheduling are essential tasks for near-optimal performance of programs for noisy quantum processors. Reliable execution of an arbitrary quantum circuit on current devices requires routing methods that overcome connectivity limitations while meeting data locality requirements. However, current devices also express highly variable noise levels in both the quantum gates and quantum registers. This requires any routing algorithm to be adaptive to both the circuit and the operating conditions. We demonstrate near-optimal routing methods of noisy quantum states that minimize the overall error of data movement while also limiting the computational complexity of routing decisions. We evaluate our methods against the noise characteristics of a 20-qubit superconducting quantum processor.
Routing plays an important role in programming noisy, intermediate-scale quantum (NISQ) devices, where limited connectivity in the register is overcome by swapping quantum information between locations. However, routing a quantum state using noisy gates introduces non-trivial noise dynamics, and deciding on an optimal route to minimize accumulated error requires estimates of the expected state fidelity. Here we validate a model for state-dependent routing dynamics in a NISQ processor based on correlated binary noise. We develop a composable, state-dependent noise model for CNOT and SWAP operations that can be characterized efficiently using pair-wise experimental measurements, and we compare model predictions with tomographic state reconstructions recovered from a quantum device. These results capture the state-dependent routing dynamics that are needed to guide routing decisions for near-real time operation of NISQ devices.
To execute a quantum program, it has to be compiled for execution on the target quantum processor. The program is first converted into a logical circuit composed of elementary gates supported by the target processor. Most often the logical circuit cannot be executed directly on the quantum processor due to the limited connectivity between the physical qubits of the processor. So, a quantum compiler needs to perform qubit routing by inserting auxiliary gates to execute operations like SWAP, MOVE, and BRIDGE in order to satisfy the connectivity constraint. Qubit routing yields a physical circuit that can be executed on the target processor. Finally, the physical circuit still has to be scheduled considering the gate delays and the control constraints imposed by the shared classical control electronics of the quantum processor. For noisy intermediate-scale quantum processors, it is important to minimize the latency of the final scheduled physical circuit. However, solving qubit routing without considering gate delays and control constraints will inevitably lead to suboptimal final results. Here we propose a control and timing-aware qubit routing algorithm, CTQr, considering gate delays and control constraints. Moreover, CTQr performs gate merging on the fly in order to minimize the final circuit latency. The experimental results show that CTQr outperforms the state-of-art approach with 11.2%, 8.8%, and 54.6% average reduction in the circuit latency, number of additional gates, and execution time, respectively.
Quantum computation promises to advance a wide range of computational tasks. However, current quantum hardware suffers from noise and is too small for error correction. Thus, accurately utilizing noisy quantum computers strongly relies on noise characterization, mitigation, and suppression. Crucially, these methods must also be efficient in terms of their classical and quantum overhead. Here, we efficiently characterize and mitigate crosstalk noise, which is a severe error source in, for example, cross-resonance based superconducting quantum processors. For crosstalk characterization, we develop a simplified measurement experiment. Furthermore, we analyze the problem of optimal experiment scheduling and solve it for common hardware architectures. After characterization, we mitigate noise in quantum circuits by a noise-aware qubit routing algorithm. Our integer programming algorithm extends previous work on optimized qubit routing by swap insertion. We incorporate the measured crosstalk errors in addition to other, more easily accessible noise data in the objective function. Furthermore, we strengthen the underlying integer linear model by proving a convex hull result about an associated class of polytopes, which has applications beyond this work. We evaluate the proposed method by characterizing crosstalk noise for two chips with up to 127 qubits and leverage the resulting data to improve the approximation ratio of the Quantum Approximate Optimization Algorithm by up to 10% compared with other established noise-aware routing methods. Our work clearly demonstrates the gains of including noise data when mapping abstract quantum circuits to hardware native ones. History: Accepted by Giacomo Nannicini, Area Editor for Quantum Computing and Operations Research. Accepted for Special Issue on Quantum Computing. Funding: This work was supported by Bavarian state government; Bayerische Staatsministerium für Wirtschaft, Landesentwicklung und Energie. Supplemental Material: The software that supports the findings of this study is available within the paper and its Supplemental Information ( https://pubsonline.informs.org/doi/suppl/10.1287/ijoc.2024.0551 ) as well as from the IJOC GitHub software repository ( https://github.com/INFORMSJoC/2024.0551 ). The complete IJOC Software and Data Repository is available at https://informsjoc.github.io/ .
As quantum hardware increases in complexity, successful algorithmic execution relies more heavily on awareness of existing device constraints. In this work we focus on the problem of routing quantum information across the machine to overcome the limited connectivity of quantum hardware. Previous approaches address the problem for each two-qubit gate separately and then impose the compatibility of the different routes. Here we shift the focus onto the set of all routing operations that are possible at any given time and favor those that most benefit the global pattern of two-qubit gates. We benchmark our optimization technique by scheduling variational algorithms for transmon chips. Finally we apply our scheduler to the design problem of quantifying the impact of manufacturing decisions. Specifically, we address the number of distinct qubit frequencies in superconducting architectures and how they affect the algorithmic performance of the quantum Fourier transform.
Quantum computers with a limited qubit connectivity require inserting SWAP gates for qubit routing, which increases gate execution errors and the impact of environmental noise due to an overhead in circuit depth. In this work, we benchmark various routing techniques considering random quantum circuits on one-dimensional and square lattice connectivities, employing both analytical and numerical methods. We introduce circuit fidelity as a comprehensive metric that captures the effects of SWAP and circuit depth overheads. Leveraging a novel approach based on the SABRE algorithm, we achieve up to 84% higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.
The variational quantum imaginary time-evolution algorithm is efficient in finding the ground state of a quantum Hamiltonian. This algorithm involves solving a system of linear equations in a classical computer and the solution is then used to propagate a quantum wave function. Here, we show that owing to the noisy nature of current quantum processors, such a quantum algorithm or the family of quantum algorithms will require single- and two-qubit gates with very low error probability to produce reliable results. Failure to meet such a condition will result in erroneous quantum data propagation even for a relatively small quantum circuit ansatz. Specifically, we provide the upper bounds on how the relative error in variational parameters' propagation scales with the probability of noise in quantum hardware. We also present an exact expression of how the relative error in variational parameter propagation scales with the probability of partially depolarizing noise.