Table of Quantum Operators and Core Circuits

Jack D. Hidary

Vicente López-Oliva, Badía Contelles Jose M., Maribel Castillo Catalán

Classical simulation remains essential for the development of quantum algorithms; however, traditional matrix-based methods struggle with scalability. While the Fast Tensor Decision Diagram (FTDD) framework offers a hybrid approach by combining the strengths of Tensor Networks and Decision Diagrams (DDs) for memory-efficient simulation, its core operations are often bottlenecked by memory management structures. Our primary motivation is to address the high computational and spatial cost associated with the hash tables, as well as to simplify the complexity of the simulation workflow. This work introduces systematic, low-level optimizations to the framework. Our main contribution is the enhancement of the memory management layer for the internal tables. We implemented a node reuse mechanism and designed a controlled strategy for hash table growth. These improvements minimize the memory footprint and reduce the costly hashing overhead inherent in DD-based simulators. We performed a thorough experimental analysis using a diverse set of quantum circuits, which were characterized by well-established metrics. Experimental results demonstrate that our enhancements improve the tool's performance and scalability. Notably, these advancements enable the simulation of complex circuits, such as Quantum Fourier Transform, with hundreds of qubits, on a standard server with 2-Tb of memory.

Stanley Gudder

Ivan B. Djordjević

Ömercan Susam, Şuayb S. Arslan

Rising popularity of quantum computers in the last decade resulted in increased interest paid to reversible circuit synthesis process. In this work, a popular essential function-based synthesis algorithm known in the literature is parallelized using openMP library. Contrary to conventional way, essential functions are synthesized when needed without keeping a table-lookup library. When the reversible circuit is synthesized in parallel using a double core processor (4 active threads with hyperthearding technology), around 2.6 speed-up is demonstrated relative to the performance of serial synthesis work. Comparison between serial and parallel synthesis by using common benchmark circuits demonstrated that the performance of the proposed parallel synthesis is always better in the overall operation work load.

Alexei Kitaev, Alexander Khanievich Shen', M. Vyalyi