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IEEE International Conference on Acoustics Speech and Signal Processing

Fourier domain decoding algorithm of non-binary LDPC codes for parallel implementation

Kenta Kasai, K. Sakaniwa

Published May 1, 2011• 4 citations
Publisher

Abstract

For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worse, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

DOI
10.1109/icassp.2011.5946358

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For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worse, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.
For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.
In this paper, an improved decoding algorithm for Non-binary low density parity check (NB-LDPC) codes with low decoding complexity and suitable for field-programmable gate array (FPGA) implementation is proposed, which is a mixed logarithmic domain FFT-BP decoding algorithm (Mixed Log-FFT-BP) for the problem of high complexity of the existing decoding algorithms for Non-binary LDPC codes. The algorithm combines the traditional Log-BP algorithm with the FFT-BP algorithm, and simplifies the update of the check nodes in the iterative decoding process. A large number of convolution operations are converted into multiplication operations in frequency domain by using FFT transform and IFFT transform. The multiplication of the original FFT-BP algorithm is converted into the addition and look-up table operations in the logarithmic domain. Then, the logarithm of the probability information is directly solved, so that it can be decoded in the logarithmic domain, which saves the computation of the log likelihood ratio, and then reduces the complexity. Simulation results show that under the additive Gauss white noise channel, when the bit error rate is 10-5, compared with BP algorithm, Log-Bp algorithm and FFT-BP algorithm, the performance of Mixed Log-FFT-BP algorithm is not decreased, and all of them remain within the range of 0.1-0.2dB.
In this paper, an improved low-complexity sum-product decoding algorithm is presented for low-density parity-check (LDPC) codes. In the proposed algorithm, reduction in computational complexity is achieved by utilizing fast Fourier transform (FFT) with time shift in the check node process. The improvement in the decoding performance is achieved by utilizing an optimized integer constant in the variable node process. Simulation results show that the proposed algorithm achieves an overall coding gain improvement ranging from 0.04 to 0.46 dB. Moreover, when compared with the sum-product algorithm (SPA), the proposed decoding algorithm can achieve a reduction of 42%–67% of the total number of arithmetic operations required for the decoding process.
Low-Density Parity-Check (LDPC) codes have gained significant popularity recently and have been recommended for various wireless standards of the future. Non-binary LDPC codes provide all the well-known advantages of binary LDPC codes but allow for much shorter block lengths. The sum-product decoding algorithm for non-binary LDPC codes is too complex for efficient implementation. Hence, we have represented the sum-product algorithm in a novel log-domain form in terms of operators defined earlier in literature. This form greatly simplifies the key step in the check-node processing and allows us to replace a max* operation in the decoder by a max operation. This leads to a sub-optimal decoding algorithm which we propose in this paper.
This contribution deals with the comparison of the sum-product algorithm (SPA) and its log-domain version (log-SPA) for decoding LDPC (low density parity check) codes over general binary extension fields. For both algorithms, we determine their computational complexity based on the number of real-valued operations and investigate their sensitivity to quantization effects. Whereas the log-SPA yields the shorter decoding time in the case of binary LDPC codes, we point out that increasing the field size tends to favor the SPA, especially when a multiplication takes only slightly more time than an addition. Further, we show that log-SPA requires fewer quantization levels and suffers less from a quantization induced error-floor.